// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dq.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dq__A9__F259

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx120x/flash/bwd_kernel_dq.zip)xyzw" };
#else
{ R"xyzw(amd-gfx120x/flash/bwd_kernel_dq.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx1201)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0x5de833c0u, 0xdbd83f5cu, 650, 292 }, // 5de833c0dbd83f5c = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x503ff8a9u, 0xde3eecbdu, 650, 478 }, // 503ff8a9de3eecbd = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x9de9bb5du, 0x700b3c29u, 650, 438 }, // 9de9bb5d700b3c29 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xe18f2da3u, 0xcc14c5d5u, 843, 398 }, // e18f2da3cc14c5d5 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x7b669c33u, 0x16242382u, 518, 292 }, // 7b669c3316242382 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x66dfafe7u, 0x7e14bdd6u, 518, 683 }, // 66dfafe77e14bdd6 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x6449ccefu, 0xb8586ceau, 518, 398 }, // 6449ccefb8586cea = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x6df7ab5cu, 0x6ae24f19u, 518, 723 }, // 6df7ab5c6ae24f19 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x883168e0u, 0xfe5dd694u, 518, 478 }, // 883168e0fe5dd694 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xa8871e20u, 0x0480358au, 518, 763 }, // a8871e200480358a = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xa69c4a8au, 0x48ffda26u, 518, 438 }, // a69c4a8a48ffda26 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xf3518e7bu, 0xf1baef8du, 518, 803 }, // f3518e7bf1baef8d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x7cfa6887u, 0x01faaafeu, 551, 292 }, // 7cfa688701faaafe = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x7c8ce26fu, 0xc0d63f2du, 551, 398 }, // 7c8ce26fc0d63f2d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xabbbf97au, 0x9d92adcau, 551, 478 }, // abbbf97a9d92adca = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x400c2cc8u, 0xde47241du, 551, 438 }, // 400c2cc8de47241d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x4fb86d90u, 0x17871969u, 584, 292 }, // 4fb86d9017871969 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x03e918adu, 0xa1359b69u, 584, 683 }, // 03e918ada1359b69 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xd7e46aaeu, 0x4eec76d2u, 584, 763 }, // d7e46aae4eec76d2 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xc5932d67u, 0x2a84e766u, 584, 803 }, // c5932d672a84e766 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xa7c3d230u, 0x71c68810u, 617, 683 }, // a7c3d23071c68810 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x9d6e08a9u, 0xdacf28feu, 617, 723 }, // 9d6e08a9dacf28fe = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x3e134fecu, 0xcc4f1baau, 617, 763 }, // 3e134feccc4f1baa = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x1fee2cc3u, 0x5d0062c2u, 617, 803 }, // 1fee2cc35d0062c2 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=80;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1201
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dq_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dq_packed_string);

static int8_t lut[1][10][10] =
{
// GPU gfx1201_mod0
{{ 3, 7, 6,10, 8, 8, 8, 6, 8,10},
 { 0,17,17,19, 7, 9, 9, 9, 7, 9},
 { 0, 2, 2, 5,16,16,16,16,16,16},
 { 1, 2, 0, 7, 9,16,16,11,11, 9},
 { 6, 1, 5, 7,11,16,16,16,22,22},
 { 4,14,14,18,17,16,17,23,11, 9},
 { 4,12,14,14,17, 8, 4,18, 8,20},
 {14,15,13,14,12,16,16,22,23,21},
 {12,15,12,15,16,13,16,23,22,20},
 {13,15,12, 8,16, 4,10,23, 8,23}}
// End of GPU gfx1201_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDqContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDqContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dq__A9__F259 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 1;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*bf16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = 0
// Window_right = 0
// BLOCK_DMODEL = 80
// CAUSAL_TYPE = 0
// ENABLE_DROPOUT = False
// PADDED_HEAD = True
// BIAS_TYPE = 1

// ('SELECT * FROM FLASH$bwd_kernel_dq WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx1201_mod0', 'torch.bfloat16', 80, 0, False, False, 1])

// vim: set fileencoding=utf-8

