// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dq.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dq__A5__F12

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx115x/flash/bwd_kernel_dq.zip)xyzw" };
#else
{ R"xyzw(amd-gfx115x/flash/bwd_kernel_dq.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx1150)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0x56166278u, 0xc9536750u, 650, 292 }, // 56166278c9536750 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1150
    { 0xde5598c4u, 0x532d005fu, 650, 398 }, // de5598c4532d005f = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x73300859u, 0x148679eau, 650, 723 }, // 73300859148679ea = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1150
    { 0x1b134575u, 0xe6d4a532u, 650, 478 }, // 1b134575e6d4a532 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x3b260479u, 0xbc80b0f9u, 650, 763 }, // 3b260479bc80b0f9 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1150
    { 0xb7f5152du, 0x2a9e03f7u, 843, 292 }, // b7f5152d2a9e03f7 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1150
    { 0xb9c0b035u, 0x2ae179f1u, 843, 398 }, // b9c0b0352ae179f1 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x6d5ee149u, 0x185fa410u, 843, 438 }, // 6d5ee149185fa410 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1150
    { 0xa5843f72u, 0xd928b397u, 518, 292 }, // a5843f72d928b397 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x87a920e9u, 0x1cd3f2a7u, 518, 398 }, // 87a920e91cd3f2a7 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x85f97132u, 0xe2ab2055u, 518, 723 }, // 85f97132e2ab2055 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1150
    { 0x40000668u, 0x6d3efe75u, 518, 478 }, // 400006686d3efe75 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1150
    { 0xba993287u, 0xa30b617fu, 518, 438 }, // ba993287a30b617f = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x68bac915u, 0xe964269au, 551, 292 }, // 68bac915e964269a = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x5c3f19bfu, 0x7a8d8d35u, 551, 398 }, // 5c3f19bf7a8d8d35 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x3c46d85bu, 0xa73f4d32u, 584, 292 }, // 3c46d85ba73f4d32 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x21a67d3bu, 0x4297f41bu, 584, 398 }, // 21a67d3b4297f41b = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x3735d2a8u, 0x4973a7e1u, 584, 478 }, // 3735d2a84973a7e1 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x900fd54eu, 0xeeb87821u, 584, 438 }, // 900fd54eeeb87821 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1150
    { 0xee6f6f6bu, 0x58f0b88cu, 617, 292 }, // ee6f6f6b58f0b88c = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1150
    { 0x49cb6249u, 0x845a13b2u, 617, 398 }, // 49cb6249845a13b2 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1150
    { 0xff3e2401u, 0x1ecec990u, 617, 478 }, // ff3e24011ecec990 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1150
    { 0xddca4111u, 0x00ed4d54u, 617, 438 }, // ddca411100ed4d54 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1150
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dq_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dq_packed_string);

static int8_t lut[1][8][8] =
{
// GPU gfx1150_mod0
{{ 7,14, 2, 3, 0,14, 0, 6},
 { 0,16, 8,10, 8,12, 8, 8},
 { 1,10, 9, 9, 9,12,16,18},
 { 4,12,11, 9, 9, 8, 9,16},
 { 3, 8,12, 9, 9,19,22,22},
 {13,11, 8,16,22,22,22,22},
 { 5,14,17,21,20,20,22,22},
 {14,13,18,16,16,15,20,19}}
// End of GPU gfx1150_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDqContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDqContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dq__A5__F12 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dq__lut_lambda__1(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dq__lut_lambda__1(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 5;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*fp16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// stride_bz = 0
// stride_bh = 0
// stride_bm = 0
// stride_dbz = 0
// stride_dbh = 0
// stride_dbm = 0
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = "fp32"
// philox_seed_ptr = "*u64"
// philox_offset2 = "u64"
// Window_left = "i32"
// Window_right = "i32"
// BLOCK_DMODEL = 16
// CAUSAL_TYPE = 3
// ENABLE_DROPOUT = True
// PADDED_HEAD = False
// BIAS_TYPE = 0

// ('SELECT * FROM FLASH$bwd_kernel_dq WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx1100_mod0', 'torch.float16', 16, 3, True, False, 0])

// vim: set fileencoding=utf-8

