// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dk_dv.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dk_dv__A0__F192

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 8})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 8 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx950/flash/bwd_kernel_dk_dv.zip)xyzw" };
#else
{ R"xyzw(amd-gfx950/flash/bwd_kernel_dk_dv.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx950)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0xdd32e3dau, 0xb30303a2u, 0, 186 }, // dd32e3dab30303a2 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0xf2394567u, 0x0b72dd80u, 0, 33 }, // f23945670b72dd80 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0x152ea0ceu, 0x4d8ffc14u, 0, 73 }, // 152ea0ce4d8ffc14 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0xf0804b9au, 0x4f6321acu, 0, 113 }, // f0804b9a4f6321ac = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0xdfce213eu, 0xa1fd021eu, 153, 186 }, // dfce213ea1fd021e = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0xf4f25ffau, 0xdd527700u, 153, 33 }, // f4f25ffadd527700 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0xd5b14679u, 0x3782a4cdu, 153, 73 }, // d5b146793782a4cd = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0x13946217u, 0x56600799u, 153, 113 }, // 1394621756600799 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0x9062b5d9u, 0xd97cb41bu, 226, 73 }, // 9062b5d9d97cb41b = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0x91e4afc2u, 0x872d6845u, 259, 186 }, // 91e4afc2872d6845 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0x28be9241u, 0x06979858u, 259, 358 }, // 28be924106979858 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx950
    { 0xa83801c3u, 0x7c8225e8u, 259, 33 }, // a83801c37c8225e8 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0x9ce8faf1u, 0x24e2a4e7u, 259, 73 }, // 9ce8faf124e2a4e7 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0x120a38b5u, 0xf69ed729u, 259, 113 }, // 120a38b5f69ed729 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0x5335ee87u, 0x91e35a40u, 292, 73 }, // 5335ee8791e35a40 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0x3b75d0e0u, 0xa7b8e395u, 292, 113 }, // 3b75d0e0a7b8e395 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0x1915954au, 0xdffa6b67u, 325, 73 }, // 1915954adffa6b67 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=16;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dk_dv_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dk_dv_packed_string);

static int8_t lut[1][10][10] =
{
// GPU gfx950_mod0
{{ 0, 2, 0, 3, 0, 2, 1, 2, 8,16},
 { 4, 4, 7, 4, 4, 4, 5, 6,14,16},
 {13,10,10,13,10, 9,11, 6,15,16},
 {12,11,12,13,13,13,12,12,15,16},
 {11,13,11,11,13, 9,11,12,14,16},
 {13,13,13,13,13, 9,13,12,14,16},
 {13,13, 9,11,11, 9,13,12,14,16},
 {13,13,13,13,13,13,12,12,14,16},
 {13,13,13,13,13,13,13,12,14,16},
 {13,13,13,13,13,13,13,13,11,13}}
// End of GPU gfx950_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDkDvContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDkDvContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dk_dv__A0__F192 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dk_dv__lut_lambda__0(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dk_dv__lut_lambda__0(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 0;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*bf16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// stride_bz = 0
// stride_bh = 0
// stride_bm = 0
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = 0
// Window_right = 0
// BLOCK_DMODEL = 16
// CAUSAL_TYPE = 0
// ENABLE_DROPOUT = False
// PADDED_HEAD = False
// BIAS_TYPE = 0

// ('SELECT * FROM FLASH$bwd_kernel_dk_dv WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx950_mod0', 'torch.bfloat16', 16, 0, False, False, 0])

// vim: set fileencoding=utf-8

