// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dq.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dq__A10__F81

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx120x/flash/bwd_kernel_dq.zip)xyzw" };
#else
{ R"xyzw(amd-gfx120x/flash/bwd_kernel_dq.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx1200)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0x4a11d99fu, 0xf0777676u, 650, 292 }, // 4a11d99ff0777676 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x0d4edd4au, 0x0742778du, 650, 398 }, // 0d4edd4a0742778d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x50b761b4u, 0x61e77e08u, 650, 478 }, // 50b761b461e77e08 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x51cc5cfau, 0xb2663ea3u, 650, 438 }, // 51cc5cfab2663ea3 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1200
    { 0xbff38a29u, 0xb69758afu, 843, 292 }, // bff38a29b69758af = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x40184c5au, 0x3260f350u, 518, 292 }, // 40184c5a3260f350 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x5ac6f707u, 0x38a01b88u, 518, 683 }, // 5ac6f70738a01b88 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1200
    { 0x650f3e38u, 0x6f95a206u, 518, 398 }, // 650f3e386f95a206 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x99f9c804u, 0xa40a9fc9u, 518, 723 }, // 99f9c804a40a9fc9 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1200
    { 0xd8eab5cdu, 0x02fc0b8fu, 518, 478 }, // d8eab5cd02fc0b8f = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x7845b2ecu, 0xbefb9447u, 518, 763 }, // 7845b2ecbefb9447 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1200
    { 0x2486ef2eu, 0x4037fad6u, 518, 438 }, // 2486ef2e4037fad6 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x38b612e4u, 0x501601b9u, 518, 803 }, // 38b612e4501601b9 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1200
    { 0xc72a42a5u, 0xba2c290bu, 551, 292 }, // c72a42a5ba2c290b = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1200
    { 0xf360c74fu, 0x5463a44eu, 551, 398 }, // f360c74f5463a44e = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1200
    { 0xa49442e5u, 0x2c24e945u, 551, 478 }, // a49442e52c24e945 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x0cd8049fu, 0x81c7dea8u, 551, 438 }, // 0cd8049f81c7dea8 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1200
    { 0x32381be2u, 0xd6f62425u, 584, 683 }, // 32381be2d6f62425 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1200
    { 0xa5c5942au, 0xcfcb3357u, 584, 763 }, // a5c5942acfcb3357 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1200
    { 0x1012749bu, 0x6a0397c6u, 617, 723 }, // 1012749b6a0397c6 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1200
    { 0xd750af3au, 0x6c2d2a26u, 617, 763 }, // d750af3a6c2d2a26 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=96;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1200
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dq_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dq_packed_string);

static int8_t lut[1][10][10] =
{
// GPU gfx1200_mod0
{{ 4, 9, 7, 9, 9, 7,11, 7, 9, 9},
 { 2,18,17,17,12, 6, 8, 6,12,10},
 { 1, 0, 2,12,12, 6, 6,12,12, 6},
 { 2, 0, 2, 8, 6, 8, 6, 6, 6, 8},
 { 7, 3, 6,10, 6,12, 6,12, 6, 8},
 {10,14,15,12, 6,10, 6, 8, 8, 6},
 {15,13,16,13,16,11, 9,17, 7,19},
 {13,13,16,14,14,16,14, 9,17,20},
 {16,15,14,13,15,14,11,19, 5,19},
 {15,14, 9,11,15, 9, 5, 5, 5, 7}}
// End of GPU gfx1200_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDqContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDqContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dq__A10__F81 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 1;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*fp16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = 0
// Window_right = 0
// BLOCK_DMODEL = 96
// CAUSAL_TYPE = 0
// ENABLE_DROPOUT = False
// PADDED_HEAD = False
// BIAS_TYPE = 1

// ('SELECT * FROM FLASH$bwd_kernel_dq WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx1201_mod0', 'torch.float16', 96, 0, False, False, 1])

// vim: set fileencoding=utf-8

