// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dq.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dq__A9__F250

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx120x/flash/bwd_kernel_dq.zip)xyzw" };
#else
{ R"xyzw(amd-gfx120x/flash/bwd_kernel_dq.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx1201)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0x0a284033u, 0xcc4ccb3eu, 650, 292 }, // 0a284033cc4ccb3e = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x386a3182u, 0xbd543899u, 650, 398 }, // 386a3182bd543899 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x82d56864u, 0x46310c29u, 650, 478 }, // 82d5686446310c29 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x5a99d5c3u, 0xd58388d7u, 650, 438 }, // 5a99d5c3d58388d7 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x2428a40au, 0xc7f66fa2u, 650, 803 }, // 2428a40ac7f66fa2 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xc0f4d7b1u, 0xed4523d2u, 843, 683 }, // c0f4d7b1ed4523d2 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x7c985ff2u, 0xa1049148u, 518, 292 }, // 7c985ff2a1049148 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xd373783bu, 0x3a55cc6bu, 518, 683 }, // d373783b3a55cc6b = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x84942fa8u, 0xe69d9867u, 518, 398 }, // 84942fa8e69d9867 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xe5554f8eu, 0xaefc7b0bu, 518, 723 }, // e5554f8eaefc7b0b = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x7b0612f8u, 0x15573e27u, 518, 478 }, // 7b0612f815573e27 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x255e183cu, 0x4ad41b86u, 518, 763 }, // 255e183c4ad41b86 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x1e00a6f7u, 0x3e4dfdb8u, 518, 438 }, // 1e00a6f73e4dfdb8 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x38a989c8u, 0xbe9976aeu, 518, 803 }, // 38a989c8be9976ae = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x34ff574cu, 0xb900e3feu, 551, 292 }, // 34ff574cb900e3fe = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x1244c383u, 0x09dc7898u, 584, 292 }, // 1244c38309dc7898 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xb4bfa93bu, 0xee9c055bu, 584, 683 }, // b4bfa93bee9c055b = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xdf82fcabu, 0xd75d0e30u, 584, 398 }, // df82fcabd75d0e30 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x8e74ac75u, 0xfec6167du, 584, 478 }, // 8e74ac75fec6167d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xf4a8c8ccu, 0x4fe45e59u, 584, 438 }, // f4a8c8cc4fe45e59 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xd51ee8a8u, 0xa1875d56u, 617, 292 }, // d51ee8a8a1875d56 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x40c3e3a4u, 0xf343ad8du, 617, 398 }, // 40c3e3a4f343ad8d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x38b9638eu, 0x0d902b1du, 617, 723 }, // 38b9638e0d902b1d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x892a97deu, 0x79b2f0a5u, 617, 803 }, // 892a97de79b2f0a5 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1201
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dq_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dq_packed_string);

static int8_t lut[1][10][10] =
{
// GPU gfx1201_mod0
{{ 0, 2, 2, 1, 1, 1, 2, 0, 3, 2},
 { 2, 6,12,10,10,12,11, 6, 6,12},
 { 4, 8, 6, 6,23, 6,10,12,22, 6},
 { 2,10, 6,10, 6, 6, 8,12,10,10},
 { 3,13, 9, 6, 8, 8, 6,12,12,10},
 { 1, 7, 8,17,19,20,20,21,21,20},
 {14,15,17,18,17,19,20,20,20,20},
 {18,17,17,18,15,17,18,17,19,18},
 { 2,16,17,18,15,18,17,20,20,19},
 { 5,10, 8,18,19,19,20,20,20,20}}
// End of GPU gfx1201_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDqContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDqContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dq__A9__F250 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 4;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*bf16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// stride_bz = 0
// stride_bh = 0
// stride_bm = 0
// stride_dbz = 0
// stride_dbh = 0
// stride_dbm = 0
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = "i32"
// Window_right = "i32"
// BLOCK_DMODEL = 64
// CAUSAL_TYPE = 3
// ENABLE_DROPOUT = False
// PADDED_HEAD = True
// BIAS_TYPE = 0

// ('SELECT * FROM FLASH$bwd_kernel_dq WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx1201_mod0', 'torch.bfloat16', 64, 3, False, False, 0])

// vim: set fileencoding=utf-8

