// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dk_dv.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dk_dv__A0__F56

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 8 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx950/flash/bwd_kernel_dk_dv.zip)xyzw" };
#else
{ R"xyzw(amd-gfx950/flash/bwd_kernel_dk_dv.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx950)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0xfca89657u, 0xe6c32abfu, 0, 33 }, // fca89657e6c32abf = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0x4b181bd1u, 0x654dcfdeu, 0, 73 }, // 4b181bd1654dcfde = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0x89222f88u, 0xba705195u, 0, 113 }, // 89222f88ba705195 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0x2c8dd469u, 0x3f15baa5u, 153, 186 }, // 2c8dd4693f15baa5 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0xb2a5d791u, 0xed41a532u, 153, 358 }, // b2a5d791ed41a532 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx950
    { 0x68fe252cu, 0x5a492a39u, 153, 33 }, // 68fe252c5a492a39 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0x4b719e46u, 0x49c5b0f7u, 153, 398 }, // 4b719e4649c5b0f7 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx950
    { 0xffe9fd38u, 0x76ddda4bu, 153, 73 }, // ffe9fd3876ddda4b = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0x7ef04eb6u, 0xd47f22a0u, 153, 113 }, // 7ef04eb6d47f22a0 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0x9f611d34u, 0x70c9d532u, 153, 478 }, // 9f611d3470c9d532 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx950
    { 0x90110635u, 0x09f1bbcbu, 259, 186 }, // 9011063509f1bbcb = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0x33fe3872u, 0x6b71346du, 259, 358 }, // 33fe38726b71346d = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx950
    { 0x53e59eccu, 0x1fb6bfa4u, 259, 33 }, // 53e59ecc1fb6bfa4 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0xac7b8358u, 0x33e3bf79u, 259, 398 }, // ac7b835833e3bf79 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx950
    { 0xdadf99b0u, 0xf73e25a8u, 259, 438 }, // dadf99b0f73e25a8 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx950
    { 0x7e1afd40u, 0xbe612623u, 259, 478 }, // 7e1afd40be612623 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx950
    { 0x16572f47u, 0x955c6736u, 292, 186 }, // 16572f47955c6736 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dk_dv.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dk_dv_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dk_dv_packed_string);

static int8_t lut[1][10][10] =
{
// GPU gfx950_mod0
{{ 9, 4, 4, 2, 0, 0, 6, 1, 2, 8},
 { 7, 3, 5, 7, 8, 3, 5, 5, 5, 8},
 {11,11,14,11,13,11,11,15,12, 7},
 {11,14,11,11,14,11,11,14,12, 7},
 {11,15,11,11,14,11,11,12,12,12},
 {11,11,11,14,11,14,14,12,12,15},
 {12,12,11,14,11,11,11,11,12,15},
 {10,12,10,12,12,12,10,10,12,12},
 {10,12,10,10,11,15,10,10,10,12},
 {10,12,10,10,12,10,10,10,12,16}}
// End of GPU gfx950_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDkDvContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDkDvContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dk_dv__A0__F56 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dk_dv__lut_lambda__0(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dk_dv__lut_lambda__0(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 4;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*fp16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// stride_bz = 0
// stride_bh = 0
// stride_bm = 0
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = "i32"
// Window_right = "i32"
// BLOCK_DMODEL = 64
// CAUSAL_TYPE = 3
// ENABLE_DROPOUT = False
// PADDED_HEAD = False
// BIAS_TYPE = 0

// ('SELECT * FROM FLASH$bwd_kernel_dk_dv WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx950_mod0', 'torch.float16', 64, 3, False, False, 0])

// vim: set fileencoding=utf-8

