// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dq.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dq__A4__F40

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx110x/flash/bwd_kernel_dq.zip)xyzw" };
#else
{ R"xyzw(amd-gfx110x/flash/bwd_kernel_dq.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx1103)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0x1ab15102u, 0x84c76abdu, 650, 292 }, // 1ab1510284c76abd = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x04e9087cu, 0xe74d4e62u, 650, 398 }, // 04e9087ce74d4e62 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x00f4f5e5u, 0xe4b83aa6u, 650, 478 }, // 00f4f5e5e4b83aa6 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1103
    { 0xe1019ae6u, 0x15cb0ebcu, 843, 292 }, // e1019ae615cb0ebc = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x50848292u, 0x91f1bc3au, 843, 398 }, // 5084829291f1bc3a = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x2e2bb958u, 0xdac4b554u, 843, 478 }, // 2e2bb958dac4b554 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x3e6c0f92u, 0x7f2c4c27u, 843, 438 }, // 3e6c0f927f2c4c27 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x09c51625u, 0xbabed42au, 518, 292 }, // 09c51625babed42a = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x7da5855eu, 0x0f94acc6u, 518, 398 }, // 7da5855e0f94acc6 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x5e6b9cb4u, 0x88ac8245u, 518, 478 }, // 5e6b9cb488ac8245 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1103
    { 0xbbb99f19u, 0xf375acc4u, 518, 438 }, // bbb99f19f375acc4 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x765fa204u, 0x45b95a94u, 551, 292 }, // 765fa20445b95a94 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x7018879du, 0x06300c46u, 551, 398 }, // 7018879d06300c46 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1103
    { 0xc69462ccu, 0xc091269du, 551, 478 }, // c69462ccc091269d = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x4c4e87eau, 0xa8e852f3u, 551, 438 }, // 4c4e87eaa8e852f3 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x03ff288au, 0x1ba0f22du, 584, 292 }, // 03ff288a1ba0f22d = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x928e8ec8u, 0x8fead0c7u, 584, 398 }, // 928e8ec88fead0c7 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x61efd31du, 0xa7e69d66u, 584, 723 }, // 61efd31da7e69d66 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1103
    { 0xf8add7c9u, 0x1c2c5070u, 584, 478 }, // f8add7c91c2c5070 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x40ace439u, 0xc3538d91u, 584, 438 }, // 40ace439c3538d91 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1103
    { 0x3c1ba349u, 0x28f224a1u, 617, 683 }, // 3c1ba34928f224a1 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1103
    { 0x0cfbc0beu, 0xb71af447u, 617, 803 }, // 0cfbc0beb71af447 = b2sum -l 64 <<< amd-gfx110x/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=48;CAUSAL_TYPE=3;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1103
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dq_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dq_packed_string);

static int8_t lut[1][8][8] =
{
// GPU gfx1103_mod0
{{11, 2, 1, 1, 1, 2,13,14},
 { 0,10, 8, 7, 9, 7,17,10},
 { 3,10,10, 9, 8,10, 8, 9},
 { 5, 8,19,10, 8,21,20,10},
 { 4, 9,10,15,15, 8,21,15},
 { 6, 8, 8, 9,15,15,15,15},
 { 5, 9, 7,10,10,15,15,15},
 { 6, 9,13,12,13,18,16,15}}
// End of GPU gfx1103_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDqContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDqContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dq__A4__F40 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dq__lut_lambda__1(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dq__lut_lambda__1(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 4;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*fp16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// stride_bz = 0
// stride_bh = 0
// stride_bm = 0
// stride_dbz = 0
// stride_dbh = 0
// stride_dbm = 0
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = "i32"
// Window_right = "i32"
// BLOCK_DMODEL = 48
// CAUSAL_TYPE = 3
// ENABLE_DROPOUT = False
// PADDED_HEAD = False
// BIAS_TYPE = 0

// ('SELECT * FROM FLASH$bwd_kernel_dq WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx1100_mod0', 'torch.float16', 48, 3, False, False, 0])

// vim: set fileencoding=utf-8

