## Automatically generated incremental diff
## From:   linux-2.2.17-pre16
## To:     linux-2.2.17-pre17
## Robot:  $Id: make-incremental-diff,v 1.8 2001/12/04 06:05:04 hpa Exp $

diff -urN linux-2.2.17-pre16/DAC960.patch linux/DAC960.patch
--- linux-2.2.17-pre16/DAC960.patch	Mon Dec  3 22:11:03 2001
+++ linux/DAC960.patch	Wed Dec 31 16:00:00 1969
@@ -1,52 +0,0 @@
---- linux/include/linux/pci.h-	Wed May  3 17:16:52 2000
-+++ linux/include/linux/pci.h	Thu May  4 08:19:51 2000
-@@ -558,10 +558,12 @@
- #define PCI_DEVICE_ID_PICOP_PT80C524	0x8002
- 
- #define PCI_VENDOR_ID_MYLEX		0x1069
--#define PCI_DEVICE_ID_MYLEX_DAC960P_V2	0x0001
--#define PCI_DEVICE_ID_MYLEX_DAC960P_V3	0x0002
--#define PCI_DEVICE_ID_MYLEX_DAC960P_V4	0x0010
--#define PCI_DEVICE_ID_MYLEX_DAC960P_V5	0x0020
-+#define PCI_DEVICE_ID_MYLEX_DAC960_P	0x0001
-+#define PCI_DEVICE_ID_MYLEX_DAC960_PD	0x0002
-+#define PCI_DEVICE_ID_MYLEX_DAC960_PG	0x0010
-+#define PCI_DEVICE_ID_MYLEX_DAC960_LA	0x0020
-+#define PCI_DEVICE_ID_MYLEX_DAC960_LP	0x0050
-+#define PCI_DEVICE_ID_MYLEX_DAC960_BA	0xBA56
- 
- #define PCI_VENDOR_ID_APPLE		0x106b
- #define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
-@@ -1094,6 +1096,7 @@
- #define PCI_DEVICE_ID_INTEL_82430	0x0486
- #define PCI_DEVICE_ID_INTEL_82434	0x04a3
- #define PCI_DEVICE_ID_INTEL_I960	0x0960
-+#define PCI_DEVICE_ID_INTEL_I960RN	0x0964
- #define PCI_DEVICE_ID_INTEL_82559ER	0x1209
- #define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
- #define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222
---- linux/drivers/pci/oldproc.c-	Wed May  3 17:16:43 2000
-+++ linux/drivers/pci/oldproc.c	Thu May  4 08:20:15 2000
-@@ -224,9 +224,11 @@
- 	DEVICE( X,		X_AGX016,	"ITT AGX016"),
- 	DEVICE( PICOP,		PICOP_PT86C52X,	"PT86C52x Vesuvius"),
- 	DEVICE( PICOP,		PICOP_PT80C524,	"PT80C524 Nile"),
--	DEVICE( MYLEX,		MYLEX_DAC960P_V2,"DAC960P V2"),
--	DEVICE( MYLEX,		MYLEX_DAC960P_V3,"DAC960P V3"),
--	DEVICE( MYLEX,		MYLEX_DAC960P_V4,"DAC960P V4"),
-+	DEVICE( MYLEX,		MYLEX_DAC960_P, "DAC960 P Series"),
-+	DEVICE( MYLEX,		MYLEX_DAC960_PD,"DAC960 PD Series"),
-+	DEVICE( MYLEX,		MYLEX_DAC960_PG,"DAC960 PG Series"),
-+	DEVICE( MYLEX,		MYLEX_DAC960_LP,"DAC960 LP Series"),
-+	DEVICE( MYLEX,		MYLEX_DAC960_BA,"DAC960 BA Series"),
- 	DEVICE( APPLE,		APPLE_BANDIT,	"Bandit"),
- 	DEVICE( APPLE,		APPLE_GC,	"Grand Central"),
- 	DEVICE( APPLE,		APPLE_HYDRA,	"Hydra"),
-@@ -519,6 +521,7 @@
- 	DEVICE( INTEL,		INTEL_82430,	"82430ZX Aries"),
- 	DEVICE( INTEL,		INTEL_82434,	"82434LX Mercury/Neptune"),
- 	DEVICE( INTEL,		INTEL_I960,	"i960"),
-+	DEVICE( INTEL,		INTEL_I960RN,	"i960 RN"),
- 	DEVICE( INTEL,		INTEL_82559ER,	"82559ER"),
- 	DEVICE( INTEL,		INTEL_82092AA_0,"82092AA PCMCIA bridge"),
- 	DEVICE( INTEL,		INTEL_82092AA_1,"82092AA EIDE"),
diff -urN linux-2.2.17-pre16/Documentation/Configure.help linux/Documentation/Configure.help
--- linux-2.2.17-pre16/Documentation/Configure.help	Mon Dec  3 22:11:03 2001
+++ linux/Documentation/Configure.help	Mon Dec  3 22:11:10 2001
@@ -12387,6 +12387,20 @@
 CONFIG_VIDEO_CPIA_PP_DMA
   This will use DMA if possible to reduce CPU usage.  If in doubt,
   say Y here.
+
+7-Segment Display support
+CONFIG_DISPLAY7SEG
+  This is the driver for the digital display and LED present on
+  Sun Microsystems CompactPCI models CP1400 and CP1500.
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called display7seg.o. If you want to compile it 
+  as a module, say M here and read Documentation/modules.txt.
+
+  If you do not have a CompactPCI model CP1400 or CP1500, or 
+  another UltraSPARC-IIi-cEngine boardset with digital display,
+  you should say N to this option.
    
 #
 # A couple of things I keep forgetting:
diff -urN linux-2.2.17-pre16/Makefile linux/Makefile
--- linux-2.2.17-pre16/Makefile	Mon Dec  3 22:11:03 2001
+++ linux/Makefile	Mon Dec  3 22:11:10 2001
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 2
 SUBLEVEL = 17
-EXTRAVERSION = pre16
+EXTRAVERSION = pre17
 
 ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
 
diff -urN linux-2.2.17-pre16/arch/i386/kernel/Makefile linux/arch/i386/kernel/Makefile
--- linux-2.2.17-pre16/arch/i386/kernel/Makefile	Wed Jan 20 10:18:53 1999
+++ linux/arch/i386/kernel/Makefile	Mon Dec  3 22:11:10 2001
@@ -14,7 +14,8 @@
 
 O_TARGET := kernel.o
 O_OBJS   := process.o signal.o entry.o traps.o irq.o vm86.o \
-            ptrace.o ioport.o ldt.o setup.o time.o sys_i386.o
+            ptrace.o ioport.o ldt.o setup.o time.o sys_i386.o \
+	    bluesmoke.o
 OX_OBJS  := i386_ksyms.o
 MX_OBJS  :=
 
diff -urN linux-2.2.17-pre16/arch/i386/kernel/bluesmoke.c linux/arch/i386/kernel/bluesmoke.c
--- linux-2.2.17-pre16/arch/i386/kernel/bluesmoke.c	Wed Dec 31 16:00:00 1969
+++ linux/arch/i386/kernel/bluesmoke.c	Mon Dec  3 22:11:10 2001
@@ -0,0 +1,107 @@
+/*
+ *	Machine Check Handler For PII/PIII
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <asm/processor.h> 
+#include <asm/msr.h>
+
+static int banks = 0;
+
+void mcheck_fault(void)
+{
+	int recover=1;
+	u32 alow, ahigh, high, low;
+	u32 mcgstl, mcgsth;
+	int i;
+	
+	rdmsr(0x17a, mcgstl, mcgsth);
+	if(mcgstl&(1<<0))	/* Recoverable ? */
+		recover=0;
+
+	printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x", smp_processor_id(), mcgstl, mcgsth);
+	
+	for(i=0;i<banks;i++)
+	{
+		rdmsr(0x401+i*4,low, high);
+		if(high&(1<<31))
+		{
+			if(high&(1<<29))
+				recover|=1;
+			if(high&(1<<25))
+				recover|=2;
+			printk(KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+			high&=~(1<<31);
+			if(high&(1<<27))
+			{
+				rdmsr(0x402+i*4, alow, ahigh);
+				printk("[%08x%08x]", alow, ahigh);
+			}
+			if(high&(1<<26))
+			{
+				rdmsr(0x402+i*4, alow, ahigh);
+				printk(" at %08x%08x", 
+					high, low);
+			}
+			wrmsr(0x401+i*4, low, high);
+		}
+	}
+	
+	if(recover&2)
+		panic("CPU context corrupt");
+	if(recover&1)
+		panic("Unable to continue");
+	printk(KERN_EMERG "Attempting to continue.\n");
+	mcgstl&=~(1<<2);
+	wrmsr(0x17a,mcgstl, mcgsth);
+}
+
+
+/*
+ *	This has to be run for each processor
+ */
+ 
+void mcheck_init(void)
+{
+	u32 l, h;
+	int i;
+	struct cpuinfo_x86 *c;
+	static int done=0;
+
+	c=cpu_data+smp_processor_id();
+	
+	if(c->x86_vendor!=X86_VENDOR_INTEL)
+		return;
+	
+	if(!(c->x86_capability&X86_FEATURE_MCE))
+		return;
+		
+	if(!(c->x86_capability&X86_FEATURE_MCA))
+		return;
+		
+	/* Ok machine check is available */
+	
+	if(done==0)
+		printk(KERN_INFO "Intel machine check architecture supported.\n");
+	rdmsr(0x179, l, h);
+	if(l&(1<<8))
+		wrmsr(0x17b, 0xffffffff, 0xffffffff);
+	banks = l&0xff;
+	for(i=1;i<banks;i++)
+	{
+		wrmsr(0x400+4*i, 0xffffffff, 0xffffffff); 
+	}
+	for(i=0;i<banks;i++)
+	{
+		wrmsr(0x401+4*i, 0x0, 0x0); 
+	}
+	__asm__ __volatile__ (
+		"movl %%cr4, %%eax\n\t"
+		"orl $0x40, %%eax\n\t"
+		"movl %%eax, %%cr4\n\t" : : : "eax");
+	printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
+	done=1;
+}
diff -urN linux-2.2.17-pre16/arch/i386/kernel/entry.S linux/arch/i386/kernel/entry.S
--- linux-2.2.17-pre16/arch/i386/kernel/entry.S	Wed May  3 17:16:31 2000
+++ linux/arch/i386/kernel/entry.S	Mon Dec  3 22:11:10 2001
@@ -366,6 +366,11 @@
 	pushl $ SYMBOL_NAME(do_page_fault)
 	jmp error_code
 
+ENTRY(machine_check)
+	pushl $0
+	pushl $ SYMBOL_NAME(mcheck_fault)
+	jmp error_code
+
 ENTRY(spurious_interrupt_bug)
 	pushl $0
 	pushl $ SYMBOL_NAME(do_spurious_interrupt_bug)
diff -urN linux-2.2.17-pre16/arch/i386/kernel/setup.c linux/arch/i386/kernel/setup.c
--- linux-2.2.17-pre16/arch/i386/kernel/setup.c	Mon Dec  3 22:11:03 2001
+++ linux/arch/i386/kernel/setup.c	Mon Dec  3 22:11:10 2001
@@ -917,6 +917,8 @@
 		printk(KERN_INFO "CPU serial number disabled.\n");
 	}
 
+	mcheck_init(c);
+	
 	if (c->x86_vendor == X86_VENDOR_CYRIX) {
 		cyrix_model(c);
 		return;
diff -urN linux-2.2.17-pre16/arch/i386/kernel/traps.c linux/arch/i386/kernel/traps.c
--- linux-2.2.17-pre16/arch/i386/kernel/traps.c	Mon Dec  3 22:11:03 2001
+++ linux/arch/i386/kernel/traps.c	Mon Dec  3 22:11:10 2001
@@ -109,6 +109,7 @@
 asmlinkage void reserved(void);
 asmlinkage void alignment_check(void);
 asmlinkage void spurious_interrupt_bug(void);
+asmlinkage void machine_check(void);
 
 int kstack_depth_to_print = 24;
 
@@ -702,6 +703,7 @@
 	set_trap_gate(15,&spurious_interrupt_bug);
 	set_trap_gate(16,&coprocessor_error);
 	set_trap_gate(17,&alignment_check);
+	set_trap_gate(18,&machine_check);
 	set_system_gate(SYSCALL_VECTOR,&system_call);
 
 	/* set up GDT task & ldt entries */
diff -urN linux-2.2.17-pre16/drivers/char/bttv.c linux/drivers/char/bttv.c
--- linux-2.2.17-pre16/drivers/char/bttv.c	Wed May  3 17:16:33 2000
+++ linux/drivers/char/bttv.c	Mon Dec  3 22:11:10 2001
@@ -1775,8 +1775,7 @@
                         if (v.channel>tvcards[btv->type].video_inputs)
                                 return -EINVAL;
 			bt848_muxsel(btv, v.channel);
-			if(v.norm!=VIDEO_MODE_PAL&&v.norm!=VIDEO_MODE_NTSC
-			   &&v.norm!=VIDEO_MODE_SECAM)
+			if (v.norm > (sizeof(tvnorms)/sizeof(*tvnorms)))
 				return -EOPNOTSUPP;
 			btv->win.norm = v.norm;
                         make_vbitab(btv);
diff -urN linux-2.2.17-pre16/drivers/scsi/qlogicfc.c linux/drivers/scsi/qlogicfc.c
--- linux-2.2.17-pre16/drivers/scsi/qlogicfc.c	Wed May  3 17:16:45 2000
+++ linux/drivers/scsi/qlogicfc.c	Mon Dec  3 22:11:10 2001
@@ -867,7 +867,7 @@
 
 	short param[8];
 	int i, j;
-	struct id_name_map temp[QLOGICFC_MAX_ID + 1];
+	static struct id_name_map temp[QLOGICFC_MAX_ID + 1];
 	struct isp2x00_hostdata *hostdata;
 
 	isp2x00_disable_irqs(host);
@@ -1904,9 +1904,9 @@
 #endif
 
 	hostdata->wwn = (u64) (hostdata->control_block.node_name[0]) << 56;
-	hostdata->wwn |= (u64) (hostdata->control_block.node_name[0] & 0xff00) << 48;
+	hostdata->wwn |= (u64) (hostdata->control_block.node_name[0] & 0xff00) << 40;
+	hostdata->wwn |= (u64) (hostdata->control_block.node_name[1] & 0x00ff) << 40;
 	hostdata->wwn |= (u64) (hostdata->control_block.node_name[1] & 0xff00) << 24;
-	hostdata->wwn |= (u64) (hostdata->control_block.node_name[1] & 0x00ff) << 48;
 	hostdata->wwn |= (u64) (hostdata->control_block.node_name[2] & 0x00ff) << 24;
 	hostdata->wwn |= (u64) (hostdata->control_block.node_name[2] & 0xff00) << 8;
 	hostdata->wwn |= (u64) (hostdata->control_block.node_name[3] & 0x00ff) << 8;
diff -urN linux-2.2.17-pre16/drivers/sound/Config.in linux/drivers/sound/Config.in
--- linux-2.2.17-pre16/drivers/sound/Config.in	Mon Dec  3 22:11:04 2001
+++ linux/drivers/sound/Config.in	Mon Dec  3 22:11:10 2001
@@ -17,6 +17,7 @@
   fi
 fi
 
+dep_tristate 'Crystal CS4281' CONFIG_SOUND_CS4281 $CONFIG_SOUND
 dep_tristate 'Crystal SoundFusion (CS461x)' CONFIG_SOUND_FUSION $CONFIG_SOUND
 dep_tristate 'Creative SBLive! (EMU10K1)' CONFIG_SOUND_EMU10K1 $CONFIG_SOUND
 dep_tristate 'Ensoniq AudioPCI (ES1370)' CONFIG_SOUND_ES1370 $CONFIG_SOUND
diff -urN linux-2.2.17-pre16/drivers/sound/Makefile linux/drivers/sound/Makefile
--- linux-2.2.17-pre16/drivers/sound/Makefile	Mon Dec  3 22:11:04 2001
+++ linux/drivers/sound/Makefile	Mon Dec  3 22:11:10 2001
@@ -88,6 +88,7 @@
 
 #jnx
 obj-$(CONFIG_SOUND_CMPCI)	+= cmpci.o
+obj-$(CONFIG_SOUND_CS4281)	+= cs4281.o
 obj-$(CONFIG_SOUND_ES1370)	+= es1370.o
 obj-$(CONFIG_SOUND_ES1371)	+= es1371.o
 obj-$(CONFIG_SOUND_ESSSOLO1)	+= esssolo1.o
diff -urN linux-2.2.17-pre16/drivers/sound/cs4281.c linux/drivers/sound/cs4281.c
--- linux-2.2.17-pre16/drivers/sound/cs4281.c	Wed Dec 31 16:00:00 1969
+++ linux/drivers/sound/cs4281.c	Mon Dec  3 22:11:10 2001
@@ -0,0 +1,2450 @@
+//*****************************************************************************
+//
+//      "cs4281.c" --  Cirrus Logic-Crystal CS4281 linux audio driver.
+//
+//      Copyright (C) 2000  Cirrus Logic Corp.  
+//            -- adapted from drivers by Thomas Sailer, 
+//            -- but don't bug him; Problems should go to:
+//            -- gw boynton (wesb@crystal.cirrus.com) or
+//            -- tom woller (twoller@crystal.cirrus.com).
+//
+//      This program is free software; you can redistribute it and/or modify
+//      it under the terms of the GNU General Public License as published by
+//      the Free Software Foundation; either version 2 of the License, or
+//      (at your option) any later version.
+//
+//      This program is distributed in the hope that it will be useful,
+//      but WITHOUT ANY WARRANTY; without even the implied warranty of
+//      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//      GNU General Public License for more details.
+//
+//      You should have received a copy of the GNU General Public License
+//      along with this program; if not, write to the Free Software
+//      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+//
+// Module command line parameters:
+//   none
+//
+//  Supported devices:
+//  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
+//  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
+//  /dev/midi   simple MIDI UART interface, no ioctl
+//
+//
+//
+
+// *****************************************************************************
+
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/sound.h>
+#include <linux/malloc.h>
+#include <linux/soundcard.h>
+#include <linux/pci.h>
+#include <linux/bitops.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <asm/spinlock.h>
+#include <asm/uaccess.h>
+#include <asm/hardirq.h>
+#include <linux/vmalloc.h>
+#include "dm.h"
+#include "cs4281_hwdefs.h"
+
+EXPORT_NO_SYMBOLS;
+
+#undef OSS_DOCUMENTED_MIXER_SEMANTICS
+
+// --------------------------------------------------------------------- 
+
+#ifndef PCI_VENDOR_ID_CIRRUS
+#define PCI_VENDOR_ID_CIRRUS          0x1013
+#endif
+#ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
+#define PCI_DEVICE_ID_CRYSTAL_CS4281  0x6005
+#endif
+
+#define CS4281_MAGIC  ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
+
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE < 0x02030d
+#ifdef MODULE
+#define __exit
+#define module_exit(x) void cleanup_module(void) { x(); }
+#define module_init(x) int init_module(void) { return x(); }
+#else
+#define __exit __attribute__ ((unused, __section__ (".text.init")))
+#define module_exit(x) // nothing 
+#define module_init(x) // nothing 
+#endif
+
+#define DECLARE_WAIT_QUEUE_HEAD(w) struct wait_queue *w = NULL
+#define DECLARE_WAITQUEUE(w,c) struct wait_queue w = {(c), NULL}
+#define wait_queue_head_t struct wait_queue *
+#define init_waitqueue_head(w) *(w) = 0
+#define init_MUTEX(m) *(m) = MUTEX
+#endif
+
+// MIDI buffer sizes 
+#define MIDIINBUF  500
+#define MIDIOUTBUF 500
+
+#define FMODE_MIDI_SHIFT 3
+#define FMODE_MIDI_READ  (FMODE_READ << FMODE_MIDI_SHIFT)
+#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
+
+
+struct cs4281_state {
+        // magic 
+        unsigned int magic;
+
+        // we keep the cards in a linked list 
+        struct cs4281_state *next;
+
+        // pcidev is needed to turn off the DDMA controller at driver shutdown 
+        struct pci_dev *pcidev;
+
+        // soundcore stuff 
+        int dev_audio;
+        int dev_mixer;
+        int dev_midi;
+// *wb*    int dev_dmfm;
+
+        // hardware resources 
+// *wb*    unsigned long iobase, sbbase, vcbase, ddmabase, mpubase, gpbase; // long for SPARC   
+        unsigned int pBA0phys, pBA1phys;
+        char *pBA0, *pBA1; 
+        unsigned int irq;
+	int endofbuffer;
+
+        // mixer registers 
+        struct {
+                unsigned short vol[10];
+                unsigned int recsrc;
+                unsigned int modcnt;
+                unsigned short micpreamp;
+        } mix;
+
+        // wave stuff   // Note that play & record formats must be the same *wb.
+        unsigned fmt;
+        unsigned channels;
+        unsigned rate;
+        unsigned char clkdiv;
+        unsigned ena;
+
+        spinlock_t lock;
+        struct semaphore open_sem;
+        mode_t open_mode;
+        wait_queue_head_t open_wait;
+
+        struct dmabuf {
+                void *rawbuf;            // Physical address of  
+                unsigned buforder;       // Log base 2 of 'rawbuf' size in bytes..
+                unsigned numfrag;        // # of 'fragments' in the buffer.
+                unsigned fragshift;      // Log base 2 of fragment size.
+                unsigned hwptr, swptr;
+                unsigned total_bytes;    // # bytes process since open.
+                int count;
+                unsigned error; // over/underrun 
+                wait_queue_head_t wait;
+                // redundant, but makes calculations easier 
+                unsigned fragsize;       // 2**fragshift..
+                unsigned dmasize;        // 2**buforder.
+                unsigned fragsamples;
+                // OSS stuff 
+                unsigned mapped:1;       // Buffer mapped in cs4281_mmap()?
+                unsigned ready:1;        // prog_dmabuf_dac()/adc() successful?
+                unsigned endcleared:1;
+                unsigned ossfragshift;
+                int ossmaxfrags;
+                unsigned subdivision;
+        } dma_dac, dma_adc;
+
+        // midi stuff 
+        struct {
+                unsigned ird, iwr, icnt;
+                unsigned ord, owr, ocnt;
+                wait_queue_head_t iwait;
+                wait_queue_head_t owait;
+                struct timer_list timer;
+                unsigned char ibuf[MIDIINBUF];
+                unsigned char obuf[MIDIOUTBUF];
+        } midi;
+
+};
+
+
+struct cs4281_state *devs = NULL;
+// --------------------------------------------------------------------- 
+//
+//		Hardware Interfaces For the CS4281
+//
+
+
+//******************************************************************************
+// "delayus()-- Delay for the specified # of microseconds.
+//******************************************************************************
+static void delayus(u32 delay)
+{
+	u32 j;   
+	if(delay > 9999)
+	{
+		j = (delay * HZ)/1000000;   /* calculate delay in jiffies  */
+		if(j<1) 
+			j=1;               /* minimum one jiffy. */
+		current->state = TASK_UNINTERRUPTIBLE;  
+		schedule_timeout(j);       
+	}
+	else
+		udelay(delay);
+	return;                      
+}
+
+
+//******************************************************************************
+// "cs4281_read_ac97" -- Reads a word from the specified location in the
+//               CS4281's address space(based on the BA0 register).
+//
+// 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
+// 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
+//                                            0h for reads.
+// 3. Write ACCTL = Control Register = 460h for initiating the write
+// 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
+// 5. if DCV not cleared, break and return error
+// 6. Read ACSTS = Status Register = 464h, check VSTS bit
+//****************************************************************************
+static int cs4281_read_ac97(struct cs4281_state *card, u32 offset, u32 *value)
+{
+	u32 count, status;
+
+        // Make sure that there is not data sitting
+        // around from a previous uncompleted access.
+        // ACSDA = Status Data Register = 47Ch
+	status = readl(card->pBA0+BA0_ACSDA);
+
+        // Setup the AC97 control registers on the CS4281 to send the
+        // appropriate command to the AC97 to perform the read.
+        // ACCAD = Command Address Register = 46Ch
+        // ACCDA = Command Data Register = 470h
+        // ACCTL = Control Register = 460h
+        // bit DCV - will clear when process completed
+        // bit CRW - Read command
+        // bit VFRM - valid frame enabled
+        // bit ESYN - ASYNC generation enabled
+
+        // Get the actual AC97 register from the offset
+	writel(offset - BA0_AC97_RESET, card->pBA0+BA0_ACCAD);
+	writel(0, card->pBA0+BA0_ACCDA);
+	writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN, card->pBA0+BA0_ACCTL);
+
+         // Wait for the read to occur.
+	for(count = 0; count < 10; count++)
+	{
+		// First, we want to wait for a short time.
+		udelay(25);
+
+		// Now, check to see if the read has completed.
+        	// ACCTL = 460h, DCV should be reset by now and 460h = 17h
+        	if( !(readl(card->pBA0+BA0_ACCTL) & ACCTL_DCV))
+			break;
+	}
+
+         // Make sure the read completed.
+	if(readl(card->pBA0+BA0_ACCTL) & ACCTL_DCV)
+ 	       return 1;
+
+         // Wait for the valid status bit to go active.
+	for(count = 0; count < 10; count++)
+	{
+        	// Read the AC97 status register.
+        	// ACSTS = Status Register = 464h
+        	status = readl(card->pBA0+BA0_ACSTS);
+
+		// See if we have valid status.
+        	// VSTS - Valid Status
+        	if(status & ACSTS_VSTS)
+        		break;
+		// Wait for a short while.
+        	udelay(25);
+	}
+
+         // Make sure we got valid status.
+	if(!(status & ACSTS_VSTS))
+        	return 1;
+
+	// Read the data returned from the AC97 register.
+	// ACSDA = Status Data Register = 474h
+	*value = readl(card->pBA0+BA0_ACSDA);
+
+	// Success.
+	return(0);
+}
+
+
+//****************************************************************************
+//
+// "cs4281_write_ac97()"-- writes a word to the specified location in the
+// CS461x's address space (based on the part's base address zero register).
+//
+// 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
+// 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
+// 3. Write ACCTL = Control Register = 460h for initiating the write
+// 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
+// 5. if DCV not cleared, break and return error
+//
+//****************************************************************************
+static int cs4281_write_ac97(struct cs4281_state *card, u32 offset, u32 value)
+{
+	u32 count, status;
+
+         // Setup the AC97 control registers on the CS4281 to send the
+         // appropriate command to the AC97 to perform the read.
+         // ACCAD = Command Address Register = 46Ch
+         // ACCDA = Command Data Register = 470h
+         // ACCTL = Control Register = 460h
+         // set DCV - will clear when process completed
+         // reset CRW - Write command
+         // set VFRM - valid frame enabled
+         // set ESYN - ASYNC generation enabled
+         // set RSTN - ARST# inactive, AC97 codec not reset
+
+         // Get the actual AC97 register from the offset
+
+	writel(offset - BA0_AC97_RESET, card->pBA0+BA0_ACCAD);
+	writel(value, card->pBA0+BA0_ACCDA);
+	writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN, card->pBA0+BA0_ACCTL);
+
+         // Wait for the write to occur.
+	for(count = 0; count < 10; count++)
+	{
+		// First, we want to wait for a short time.
+        	udelay(25);
+		// Now, check to see if the write has completed.
+		// ACCTL = 460h, DCV should be reset by now and 460h = 07h
+		status = readl(card->pBA0+BA0_ACCTL);
+		if(!(status & ACCTL_DCV))
+			break;
+	}
+
+        // Make sure the write completed.
+	if(status & ACCTL_DCV)
+	        return 1;
+	// Success.
+	return 0;
+}
+
+
+//******************************************************************************
+// "Init4281()" -- Bring up the part.
+//******************************************************************************
+static int cs4281_hw_init(struct cs4281_state *card)
+{
+	u32 ac97_slotid;
+	u32 temp1, temp2;
+
+	//***************************************
+	//  Set up the Sound System Configuration
+	//***************************************
+
+         // Set the 'Configuration Write Protect' register
+         // to 4281h.  Allows vendor-defined configuration
+         // space between 0e4h and 0ffh to be written.
+
+	writel(0x4281, card->pBA0+BA0_CWPR);                       // (3e0h)
+
+         // (0), Blast the clock control register to zero so that the
+         // PLL starts out in a known state, and blast the master serial
+         // port control register to zero so that the serial ports also
+         // start out in a known state.
+
+	writel(0, card->pBA0+BA0_CLKCR1);                          // (400h)
+	writel(0, card->pBA0+BA0_SERMC);                           // (420h)
+
+
+         // (1), Make ESYN go to zero to turn off
+         // the Sync pulse on the AC97 link.
+
+	writel(0, card->pBA0+BA0_ACCTL);
+	udelay(50);
+
+
+         // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
+         // the AC97 spec) and then drive it high.  This is done for non
+         // AC97 modes since there might be logic external to the CS461x
+         // that uses the ARST# line for a reset.
+
+	writel(0, card->pBA0+BA0_SPMC);                            // (3ech)
+	udelay(100);
+	writel(SPMC_RSTN, card->pBA0+BA0_SPMC);
+	delayus(50000);     // Wait 50 ms for ABITCLK to become stable.
+
+        // (3) Turn on the Sound System Clocks.
+	writel(CLKCR1_PLLP, card->pBA0+BA0_CLKCR1);                // (400h)
+	delayus(50000);     // Wait for the PLL to stabilize.
+	// Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
+	writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0+BA0_CLKCR1);
+
+        // (4) Power on everything for now..
+	writel(0x7E, card->pBA0 + BA0_SSPM);                       // (740h)
+
+        // (5) Wait for clock stabilization.
+	for(temp1=0; temp1<1000;  temp1++)
+	{
+		udelay(1000);
+		if(readl(card->pBA0+BA0_CLKCR1) & CLKCR1_DLLRDY)
+			break;
+	}
+	if(!(readl(card->pBA0+BA0_CLKCR1) & CLKCR1_DLLRDY))
+	{
+		printk(KERN_ERR "cs4281: DLLRDY failed!\n");
+		return -EIO;
+	}
+
+	// (6) Enable ASYNC generation.
+	writel(ACCTL_ESYN, card->pBA0+BA0_ACCTL);                  // (460h)
+
+	// Now wait 'for a short while' to allow the  AC97
+	// part to start generating bit clock. (so we don't
+	// Try to start the PLL without an input clock.)
+	delayus(50000);
+
+        // Set the serial port timing configuration, so that the
+        // clock control circuit gets its clock from the right place.
+	writel(SERMC_PTC_AC97, card->pBA0+BA0_SERMC);              // (420h)=2.
+
+        // (7) Wait for the codec ready signal from the AC97 codec.
+
+	for(temp1=0; temp1<1000; temp1++)
+	{
+		// Delay a mil to let things settle out and
+		// to prevent retrying the read too quickly.
+		udelay(1000);
+		if( readl(card->pBA0+BA0_ACSTS) & ACSTS_CRDY )	// If ready,  (464h)
+			break;                                  //   exit the 'for' loop.
+	}
+	if( !(readl(card->pBA0+BA0_ACSTS) & ACSTS_CRDY) )       // If never came ready,
+	{
+        	printk(KERN_ERR "cs4281: ACSTS never came ready!\n");
+        	return -EIO;                                //   exit initialization.
+	}
+
+         // (8) Assert the 'valid frame' signal so we can
+         // begin sending commands to the AC97 codec.
+	writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0+BA0_ACCTL);   // (460h)
+
+         // (9), Wait until CODEC calibration is finished.
+         // Print an error message if it doesn't.
+	for(temp1 = 0; temp1 < 1000; temp1++)
+	{
+		delayus(10000);
+		// Read the AC97 Powerdown Control/Status Register.
+		cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
+		if( (temp2 & 0x0000000F) == 0x0000000F )
+			break;
+	}
+	if ( (temp2 & 0x0000000F) != 0x0000000F )
+	{
+		printk(KERN_ERR "cs4281: Codec failed to calibrate.  Status = %.8x.\n", temp2);
+		return -EIO;
+	}
+
+         // (10), Set the serial port timing configuration, so that the
+         // clock control circuit gets its clock from the right place.
+	writel(SERMC_PTC_AC97, card->pBA0+BA0_SERMC);              // (420h)=2.
+
+
+         // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
+         // that the codec is pumping ADC data across the AC link.
+	for(temp1=0; temp1<1000; temp1++)
+	{
+        	// Delay a mil to let things settle out and
+        	// to prevent retrying the read too quickly.
+        	delayus(1000);    //(test)
+
+        	// Read the input slot valid register;  See
+        	// if input slots 3 and 4 are valid yet.
+        	if( (readl(card->pBA0+BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ) ==  (ACISV_ISV3 | ACISV_ISV4))
+			break;    // Exit the 'for' if slots are valid.
+	}
+       	// If we never got valid data, exit initialization.
+	if( (readl(card->pBA0+BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ) != (ACISV_ISV3 | ACISV_ISV4))
+	{
+       		printk(KERN_ERR "cs4281: Never got valid data!\n");
+       		return -EIO;     // If no valid data, exit initialization.
+	}
+
+	// (12), Start digital data transfer of audio data to the codec.
+	writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0+BA0_ACOSV);             // (468h)
+
+
+        //**************************************
+        // Unmute the Master and Alternate
+        // (headphone) volumes.  Set to max.
+        //**************************************
+	cs4281_write_ac97(card,BA0_AC97_HEADPHONE_VOLUME, 0);
+	cs4281_write_ac97(card,BA0_AC97_MASTER_VOLUME, 0);
+
+        //******************************************
+        // Power on the DAC(AddDACUser()from main())
+        //******************************************
+	cs4281_read_ac97(card,BA0_AC97_POWERDOWN, &temp1);
+	cs4281_write_ac97(card,BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
+
+        // Wait until we sample a DAC ready state.
+	for(temp2=0; temp2<32; temp2++)
+	{
+		// Let's wait a mil to let things settle.
+		delayus(1000);
+		// Read the current state of the power control reg.
+        	cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
+		// If the DAC ready state bit is set, stop waiting.
+		if(temp1 & 0x2)
+        		break;
+	}
+
+        //******************************************
+        // Power on the ADC(AddADCUser()from main())
+        //******************************************
+	cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
+	cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
+
+        // Wait until we sample ADC ready state.
+	for(temp2=0; temp2<32; temp2++)
+	{
+		// Let's wait a mil to let things settle.
+		delayus(1000);
+        	// Read the current state of the power control reg.
+        	cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
+		// If the ADC ready state bit is set, stop waiting.
+		if(temp1 & 0x1)
+        		break;
+	}
+	// Set up 4281 Register contents that
+	// don't change for boot duration.
+
+	// For playback, we map AC97 slot 3 and 4(Left
+	// & Right PCM playback) to DMA Channel 0.
+	// Set the fifo to be 15 bytes at offset zero.
+
+	ac97_slotid = 0x01000f00;	// FCR0.RS[4:0]=1(=>slot4, right PCM playback).
+        				// FCR0.LS[4:0]=0(=>slot3, left PCM playback).
+                                 	// FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
+	writel(ac97_slotid, card->pBA0 + BA0_FCR0);                 // (180h)
+	writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0);      // Turn on FIFO Enable.
+
+        // For capture, we map AC97 slot 10 and 11(Left
+        // and Right PCM Record) to DMA Channel 1.
+        // Set the fifo to be 15 bytes at offset sixteen.
+	ac97_slotid = 0x0B0A0f10;	// FCR1.RS[4:0]=11(=>slot11, right PCM record).
+               				// FCR1.LS[4:0]=10(=>slot10, left PCM record).
+					// FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
+	writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1);      // (184h)
+	writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1);      // Turn on FIFO Enable.
+
+        // Map the Playback SRC to the same AC97 slots(3 & 4--
+        // --Playback left & right)as DMA channel 0.
+        // Map the record SRC to the same AC97 slots(10 & 11--
+        // -- Record left & right) as DMA channel 1.
+
+	ac97_slotid = 0x0b0a0100;	// SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
+					// SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
+					// SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
+					// SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
+	writel(ac97_slotid, card->pBA0 + BA0_SRCSA);                // (75ch)
+
+        // Set 'Half Terminal Count Interrupt Enable' and 'Terminal
+        // Count Interrupt Enable' in DMA Control Registers 0 & 1.
+        // Set 'MSK' flag to 1 to keep the DMA engines paused.
+	temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK);	 // (00030001h)
+	writel(temp1, card->pBA0 + BA0_DCR0);            // (154h
+	writel(temp1, card->pBA0 + BA0_DCR1);            // (15ch)
+
+        // Set 'Auto-Initialize Control' to 'enabled'; For playback,
+        // set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
+        // for record, set Transfer Type Control to 'write transfer'.
+        // All other bits set to zero;  Some will be changed @ transfer start.
+	temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ);   // (20000018h)
+	writel(temp1, card->pBA0 + BA0_DMR0);            // (150h)
+	temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE);  // (20000014h)
+	writel(temp1, card->pBA0 + BA0_DMR1);            // (158h)
+
+        // Enable DMA interrupts generally, and
+        // DMA0 & DMA1 interrupts specifically.
+	temp1 = readl(card->pBA0 + BA0_HIMR) &  0xfffbfcff;
+	writel(temp1, card->pBA0+BA0_HIMR);
+	return 0;
+}
+
+
+//******************************************************************************
+// "cs4281_play_rate()" --
+//******************************************************************************
+static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
+{
+	u32 DACSRvalue = 1;
+
+         // Based on the sample rate, program the DACSR register.
+	if(playrate == 8000)
+        	DACSRvalue = 5;
+	if(playrate == 11025)
+		DACSRvalue = 4;
+	else if(playrate == 22050)
+        	DACSRvalue = 2;
+	else if(playrate == 44100)
+	        DACSRvalue = 1;
+	else if((playrate <= 48000) && (playrate >= 6023))
+        	DACSRvalue = 24576000/(playrate*16);
+	else if(playrate < 6023)
+		// Not allowed by open.
+		return;
+	else if(playrate > 48000)
+		// Not allowed by open.
+		return;
+         //  Write the 'sample rate select code'
+         //  to the 'DAC Sample Rate' register.
+	writel(DACSRvalue, card->pBA0 + BA0_DACSR);           // (744h)
+}
+
+//******************************************************************************
+// "cs481_record_rate()" -- Initialize the record sample rate converter.
+//******************************************************************************
+static void cs481_record_rate(struct cs4281_state *card, u32 outrate)
+{
+	u32 ADCSRvalue = 1;
+
+         //
+         // Based on the sample rate, program the ADCSR register
+         //
+	if(outrate == 8000)
+        	ADCSRvalue = 5;
+	if(outrate == 11025)
+	        ADCSRvalue = 4;
+	else if(outrate == 22050)
+		ADCSRvalue = 2;
+	else if(outrate == 44100)
+		ADCSRvalue = 1;
+	else if((outrate <= 48000) && (outrate >= 6023))
+		ADCSRvalue = 24576000/(outrate*16);
+	else if(outrate < 6023)
+	{
+		// Not allowed by open.
+		return;
+	}
+	else if(outrate > 48000)
+	{
+	        // Not allowed by open.
+	        return;
+	}
+        //  Write the 'sample rate select code
+	//  to the 'ADC Sample Rate' register.
+	writel(ADCSRvalue, card->pBA0 + BA0_ADCSR);           // (748h)
+}
+
+
+
+static void stop_dac(struct cs4281_state *s)
+{
+        unsigned long flags;
+        unsigned temp1;
+
+        spin_lock_irqsave(&s->lock, flags);
+        s->ena &= ~FMODE_WRITE;
+        temp1 = readl(s->pBA0+ BA0_DCR0) | DCRn_MSK;     
+        writel(temp1, s->pBA0+BA0_DCR0);         
+
+        spin_unlock_irqrestore(&s->lock, flags);
+}
+
+
+static void start_dac(struct cs4281_state *s)
+{
+        unsigned long flags;
+        unsigned temp1;
+
+        spin_lock_irqsave(&s->lock, flags);
+        if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
+              s->dma_dac.count > 0) && s->dma_dac.ready)      {
+                s->ena |= FMODE_WRITE;
+                temp1 = readl(s->pBA0+BA0_DCR0) & ~DCRn_MSK;     // Clear DMA0 channel mask.
+                writel(temp1, s->pBA0+BA0_DCR0);                 // Start DMA'ing.
+                writel(HICR_IEV | HICR_CHGM, s->pBA0+BA0_HICR);     // Enable interrupts.              
+        
+                writel(7, s->pBA0+BA0_PPRVC);
+                writel(7, s->pBA0+BA0_PPLVC);
+        
+        }
+        spin_unlock_irqrestore(&s->lock, flags);
+}
+
+
+static void stop_adc(struct cs4281_state *s)
+{
+        unsigned long flags;
+        unsigned temp1;
+
+        spin_lock_irqsave(&s->lock, flags);
+        s->ena &= ~FMODE_READ;
+        temp1 = readl(s->pBA0+ BA0_DCR1) | DCRn_MSK;     
+        writel(temp1, s->pBA0+BA0_DCR1);
+        spin_unlock_irqrestore(&s->lock, flags);
+}
+
+
+static void start_adc(struct cs4281_state *s)
+{
+        unsigned long flags;
+        unsigned temp1;
+
+        spin_lock_irqsave(&s->lock, flags);
+        if (!(s->ena & FMODE_READ) && (s->dma_adc.mapped
+              || s->dma_adc.count <= 
+                 (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
+              && s->dma_adc.ready)
+        {
+                s->ena |= FMODE_READ;
+                temp1 = readl(s->pBA0+BA0_DCR1) & ~ DCRn_MSK;         // Clear DMA1 channel mask bit.
+                writel(temp1, s->pBA0+BA0_DCR1);                      // Start recording
+                writel(HICR_IEV | HICR_CHGM, s->pBA0+BA0_HICR);       // Enable interrupts.
+        }
+        spin_unlock_irqrestore(&s->lock, flags);
+
+}
+
+
+// --------------------------------------------------------------------- 
+#define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)     // == 3(for PC), = log base 2( buff sz = 32k).
+#define DMABUF_MINORDER 1                       // ==> min buffer size = 8K.
+
+
+static void dealloc_dmabuf(struct dmabuf *db)
+{
+        unsigned long map, mapend;
+
+        if (db->rawbuf) {
+                // Undo prog_dmabuf()'s marking the pages as reserved 
+                mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
+                for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
+                        clear_bit(PG_reserved, &mem_map[map].flags);
+                free_pages((unsigned long)db->rawbuf, db->buforder);
+        }
+        db->rawbuf = NULL;
+        db->mapped = db->ready = 0;
+}
+
+
+static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db, int gfp_mask)
+{
+        int order;
+        unsigned bytespersec, temp1;
+        unsigned bufs, sample_shift = 0;
+        unsigned long map, mapend;
+
+        db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
+        if (!db->rawbuf) {
+                db->ready = db->mapped = 0;
+                for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
+                        if ((db->rawbuf = (void *)__get_free_pages(gfp_mask, order)))
+                                break;
+                if (!db->rawbuf)
+                        return -ENOMEM;
+                db->buforder = order;
+                // Now mark the pages as reserved; otherwise the 
+                // remap_page_range() in cs4281_mmap doesn't work.
+                // 1. get index to last page in mem_map array for rawbuf.
+                mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
+                
+                     // 2. mark each physical page in range as 'reserved'.
+                for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
+                        set_bit(PG_reserved, &mem_map[map].flags);
+        }
+        if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
+                sample_shift++;
+        if (s->channels > 1)
+                sample_shift++;
+        bytespersec = s->rate << sample_shift;
+        bufs = PAGE_SIZE << db->buforder;
+
+
+#define INTERRUPT_RATE_MS       100                      // Interrupt rate in milliseconds.
+        db->numfrag = 2;
+        temp1 = bytespersec/(1000/INTERRUPT_RATE_MS);    // Nominal frag size(bytes/interrupt)
+        db->fragshift = 8;                               // Min 256 bytes.
+        while( 1 << db->fragshift  < temp1)              // Calc power of 2 frag size.
+                db->fragshift +=1;
+        db->fragsize = 1 << db->fragshift;               
+        db->dmasize = db->fragsize * 2;
+ 
+                // If the calculated size is larger than the allocated
+                //  buffer, divide the allocated buffer into 2 fragments.
+        if(db->dmasize > bufs) {
+                db->numfrag = 2;                                 // Two fragments.
+                db->fragsize = bufs >> 1;                        // Each 1/2 the alloc'ed buffer.
+                db->fragsamples = db->fragsize >> sample_shift;  // # samples/fragment.
+                db->dmasize =  bufs;                             // Use all the alloc'ed buffer.
+                
+                db->fragshift = 0;                               // Calculate 'fragshift'.
+                temp1 = db->fragsize;                            // update_ptr() uses it 
+                while( (temp1 >>=1) > 1)                         // to calc 'total-bytes'
+                     db->fragshift +=1;                          // returned in DSP_GETI/OPTR. 
+        }
+        return 0;
+}    
+
+
+static int prog_dmabuf_adc(struct cs4281_state *s)
+{
+        unsigned long va;
+        unsigned count;      
+        int c;
+        stop_adc(s);
+        if ((c = prog_dmabuf(s, &s->dma_adc, GFP_KERNEL | GFP_DMA)))
+                return c;
+             
+        va = virt_to_bus(s->dma_adc.rawbuf);
+        
+        count = s->dma_adc.dmasize;       
+       
+        if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
+                count /= 2;                      // 16-bit.
+                        
+        if(s->channels > 1)
+                count /= 2;                      // Assume stereo.
+          
+        writel(va, s->pBA0+BA0_DBA1);            // Set buffer start address.
+        writel(count-1, s->pBA0+BA0_DBC1);       // Set count. 
+        s->dma_adc.ready = 1;
+        return 0;
+}
+
+
+static int prog_dmabuf_dac(struct cs4281_state *s)
+{
+        unsigned long va;
+        unsigned count;
+        int c;
+        stop_dac(s);
+        if ((c = prog_dmabuf(s, &s->dma_dac, GFP_KERNEL)))
+                return c;
+        memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE))
+                                   ? 0x80 : 0, s->dma_dac.dmasize);      
+
+        va = virt_to_bus(s->dma_dac.rawbuf);
+
+        count = s->dma_dac.dmasize;       
+        if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
+                count /= 2;                      // 16-bit.
+      
+        if(s->channels > 1)
+                count /= 2;                      // Assume stereo.
+           
+        writel(va, s->pBA0+BA0_DBA0);               // Set buffer start address.
+        writel(count-1, s->pBA0+BA0_DBC0);       // Set count.             
+
+        s->dma_dac.ready = 1;
+        return 0;
+}
+
+
+static void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
+{
+        if (bptr + len > bsize) {
+                unsigned x = bsize - bptr;
+                memset(((char *)buf) + bptr, c, x);
+                bptr = 0;
+                len -= x;
+        }
+        memset(((char *)buf) + bptr, c, len);
+}
+
+
+
+// call with spinlock held! 
+static void cs4281_update_ptr(struct cs4281_state *s)
+{
+        int diff;
+        unsigned hwptr, va, temp1;
+
+        // update ADC pointer 
+        if (s->ena & FMODE_READ) {
+                hwptr = readl(s->pBA0+BA0_DCA1);          // Read capture DMA address.
+                va = virt_to_bus(s->dma_adc.rawbuf);
+                //trw added fix  hwptr -= (unsigned)s->dma_adc.rawbuf;
+                hwptr -= (unsigned)va;                 
+                diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
+                s->dma_adc.hwptr = hwptr;
+                s->dma_adc.total_bytes += diff;
+                s->dma_adc.count += diff;
+                if (s->dma_adc.mapped) {
+                        if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
+                                wake_up(&s->dma_adc.wait);
+                } else {
+                        if (s->dma_adc.count > 0)
+                                wake_up(&s->dma_adc.wait);
+                }
+        }
+        // update DAC pointer 
+	//
+	// check for end of buffer, means that we are going to wait for another interrupt
+	// to allow silence to fill the fifos on the part, to keep pops down to a minimum.
+	//
+        if ( (s->ena & FMODE_WRITE) && (!s->endofbuffer) )
+	{
+                hwptr = readl(s->pBA0+BA0_DCA0);          // Read play DMA address.
+                va = virt_to_bus(s->dma_dac.rawbuf);
+                hwptr -= (unsigned)va;
+                diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
+                s->dma_dac.hwptr = hwptr;
+                s->dma_dac.total_bytes += diff;
+                if (s->dma_dac.mapped) {
+                        s->dma_dac.count += diff;
+                        if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
+                                wake_up(&s->dma_dac.wait);
+                } else {
+                        s->dma_dac.count -= diff;
+                        if (s->dma_dac.count <= 0) {
+                                s->ena &= ~FMODE_WRITE;
+                                temp1 = readl(s->pBA0+BA0_DCR0);
+			//
+			// fill with silence, and wait on turning off the DAC until interrupt routine.
+			// wait on "Poke(pBA0+BA0_DCR0, temp1 | DCRn_MSK);    // Stop Play DMA"
+			//
+				memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, 
+					s->dma_dac.dmasize); 
+				s->endofbuffer = 1;
+                        } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize
+                                                         && !s->dma_dac.endcleared) {
+                                clear_advance(s->dma_dac.rawbuf, 
+                                              s->dma_dac.dmasize, s->dma_dac.swptr,
+                                              s->dma_dac.fragsize,
+                                              (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0);
+                                s->dma_dac.endcleared = 1;
+                        }
+                        if (s->dma_dac.count < (signed)s->dma_dac.dmasize)
+                                wake_up(&s->dma_dac.wait);
+                }
+        }
+}
+
+
+// --------------------------------------------------------------------- 
+
+static void prog_codec(struct cs4281_state *s)
+{
+        unsigned long flags;
+        unsigned temp1, format;
+
+        spin_lock_irqsave(&s->lock, flags);
+        temp1 = readl(s->pBA0+BA0_DCR0);
+        writel(temp1 | DCRn_MSK, s->pBA0+BA0_DCR0);   // Stop play DMA, if active.
+        temp1 = readl(s->pBA0+BA0_DCR1);
+        writel(temp1 | DCRn_MSK, s->pBA0+BA0_DCR1);   // Stop capture DMA, if active.
+ 
+        // program sampling rates  
+        // Note, for CS4281, capture & play rates can be set independently.
+        cs481_record_rate(s, s->rate); 
+               
+        // program ADC parameters 
+        format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
+        if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
+        if(s->fmt & (AFMT_S16_BE | AFMT_U16_BE))  // Big-endian?
+                format |= DMRn_BEND;  
+                if(s->fmt & (AFMT_U16_LE  | AFMT_U16_BE)) 
+                        format |= DMRn_USIGN;         // Unsigned.      
+        }          
+        else
+                format |= DMRn_SIZE8 | DMRn_USIGN;    // 8-bit, unsigned
+        if(s->channels < 2)
+                format |= DMRn_MONO;
+
+        writel(format, s->pBA0+BA0_DMR1);       
+       
+  
+        // program DAC parameters 
+        format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
+        if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
+                if(s->fmt & (AFMT_S16_BE | AFMT_U16_BE))  
+                        format |= DMRn_BEND;          // Big Endian.
+                if(s->fmt & (AFMT_U16_LE  | AFMT_U16_BE)) 
+                        format |= DMRn_USIGN;         // Unsigned.      
+        }          
+        else
+                format |= DMRn_SIZE8 | DMRn_USIGN;    // 8-bit, unsigned
+        
+        if(s->channels < 2)
+                format |= DMRn_MONO;
+
+        writel(format, s->pBA0+BA0_DMR0);       
+        cs4281_play_rate(s, s->rate);
+
+        s->ena = 0;     // Neither writing or reading.
+        spin_unlock_irqrestore(&s->lock, flags);
+}
+
+
+// --------------------------------------------------------------------- 
+
+static const char invalid_magic[] = KERN_CRIT "cs4281: invalid magic value\n";
+
+#define VALIDATE_STATE(s)                         \
+({                                                \
+        if (!(s) || (s)->magic != CS4281_MAGIC) { \
+                printk(invalid_magic);            \
+                return -ENXIO;                    \
+        }                                         \
+})
+
+// --------------------------------------------------------------------- 
+
+
+static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd, unsigned long arg)
+{
+	// Index to mixer_src[] is value of AC97 Input Mux Select Reg.
+	// Value of array member is recording source Device ID Mask.
+        static const unsigned int mixer_src[8] = {
+                SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
+                SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
+        };
+             
+        // Index of mixtable1[] member is Device ID 
+        // and must be <= SOUND_MIXER_NRDEVICES.
+        // Value of array member is index into s->mix.vol[]
+        static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
+                [SOUND_MIXER_PCM]     = 1,   // voice 
+                [SOUND_MIXER_LINE1]   = 2,   // AUX
+                [SOUND_MIXER_CD]      = 3,   // CD 
+                [SOUND_MIXER_LINE]    = 4,   // Line 
+                [SOUND_MIXER_SYNTH]   = 5,   // FM
+                [SOUND_MIXER_MIC]     = 6,   // Mic 
+                [SOUND_MIXER_SPEAKER] = 7,   // Speaker 
+                [SOUND_MIXER_RECLEV]  = 8,   // Recording level 
+                [SOUND_MIXER_VOLUME]  = 9    // Master Volume 
+        };
+        
+        
+        static const unsigned mixreg[] = {
+                BA0_AC97_PCM_OUT_VOLUME,
+                BA0_AC97_AUX_VOLUME, 
+                BA0_AC97_CD_VOLUME, 
+                BA0_AC97_LINE_IN_VOLUME
+        };
+        unsigned char l, r, rl, rr, vidx;
+        unsigned char attentbl[11] = {63,42,26,17,14,11,8,6,4,2,0};
+        unsigned temp1;
+        int i, val;
+
+        VALIDATE_STATE(s);
+ 
+        if (cmd == SOUND_MIXER_PRIVATE1) {
+                // enable/disable/query mixer preamp 
+                get_user_ret(val, (int *)arg, -EFAULT);
+                if (val != -1) {
+                        cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
+                        temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
+                        cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
+                }
+                cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
+                val = (temp1 & 0x40) ? 1 : 0;
+                return put_user(val, (int *)arg);
+        }
+        if (cmd == SOUND_MIXER_PRIVATE2) {
+                // enable/disable/query spatializer 
+                get_user_ret(val, (int *)arg, -EFAULT);
+                if (val != -1) {
+                        temp1 = (val & 0x3f) >> 2;
+                        cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
+                        cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &temp1);
+                        cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,temp1 | 0x2000);
+                }
+                cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
+                return put_user((temp1 << 2) | 3, (int *)arg);
+        }
+        if (cmd == SOUND_MIXER_INFO) {
+                mixer_info info;
+                strncpy(info.id, "CS4281", sizeof(info.id));
+                strncpy(info.name, "Crystal CS4281", sizeof(info.name));
+                info.modify_counter = s->mix.modcnt;
+                if (copy_to_user((void *)arg, &info, sizeof(info)))
+                        return -EFAULT;
+                return 0;
+        }
+        if (cmd == SOUND_OLD_MIXER_INFO) {
+                _old_mixer_info info;
+                strncpy(info.id, "CS4281", sizeof(info.id));
+                strncpy(info.name, "Crystal CS4281", sizeof(info.name));
+                if (copy_to_user((void *)arg, &info, sizeof(info)))
+                        return -EFAULT;
+                return 0;
+        }
+        if (cmd == OSS_GETVERSION)
+                return put_user(SOUND_VERSION, (int *)arg);
+        
+        if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
+                return -EINVAL;
+        
+             // If ioctl has only the IOC_READ bit(bit 31)
+             // on, process the only-read commands. 
+        if (_IOC_DIR(cmd) == _IOC_READ) {
+                switch (_IOC_NR(cmd)) {
+                case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 
+                    cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT, &temp1);
+                    return put_user(mixer_src[temp1 & 7], (int *)arg);
+
+                case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device 
+                        return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
+                                        SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
+                                        SOUND_MASK_VOLUME | SOUND_MASK_RECLEV |
+                                        SOUND_MASK_SPEAKER, (int *)arg);
+
+                case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source 
+                        return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD 
+                                      | SOUND_MASK_VOLUME | SOUND_MASK_LINE1, (int *)arg);
+
+                case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo 
+                        return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
+                                        SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
+                                        SOUND_MASK_VOLUME | SOUND_MASK_RECLEV, (int *)arg);
+
+                case SOUND_MIXER_CAPS:
+                        return put_user(SOUND_CAP_EXCL_INPUT, (int *)arg);
+
+                default:
+                        i = _IOC_NR(cmd);
+                        if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
+                                return -EINVAL;
+                        return put_user(s->mix.vol[vidx-1], (int *)arg);
+                }
+        }
+        
+             // If ioctl doesn't have both the IOC_READ and 
+             // the IOC_WRITE bit set, return invalid.
+        if (_IOC_DIR(cmd) != (_IOC_READ|_IOC_WRITE))
+                return -EINVAL;
+        
+             // Increment the count of volume writes.
+        s->mix.modcnt++;
+             
+             // Isolate the command; it must be a write.
+        switch (_IOC_NR(cmd)) {
+        
+        case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 
+                get_user_ret(val, (int *)arg, -EFAULT);
+                i = hweight32(val);                 // i = # bits on in val.
+                if (i != 1)                         // One & only 1 bit must be on.
+                        return 0;
+                for(i=0; i<sizeof(mixer_src)/sizeof(int); i++) {
+                        if(val == mixer_src[i]) {
+                                temp1 = (i << 8) | i;  
+                                cs4281_write_ac97(s, BA0_AC97_RECORD_SELECT, temp1);
+                                return 0;
+                        }
+                }
+                return 0;
+
+        case SOUND_MIXER_VOLUME:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                l = val & 0xff;
+                if(l > 100)
+                        l = 100;                    // Max soundcard.h vol is 100.
+                if(l < 6) {
+                        rl = 63;
+                        l  = 0;
+                }
+                else 
+                        rl = attentbl[(10*l)/100];  // Convert 0-100 vol to 63-0 atten.
+                        
+                        r = (val >> 8) & 0xff;
+                        if (r > 100)
+                                r = 100;            // Max right volume is 100, too
+                        if(r < 6) {
+                                rr = 63;
+                                r  = 0;
+                        }
+                        else 
+                               rr = attentbl[(10*r)/100];   // Convert volume to attenuation.
+                
+                if ((rl > 60 ) && (rr > 60))        // If both l & r are 'low',          
+                        temp1 = 0x8000;             //  turn on the mute bit.
+                else
+                        temp1 = 0;
+                
+                temp1 |= (rl << 8) | rr;
+                
+                cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1);
+                cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1);
+
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+                s->mix.vol[8] = ((unsigned int)r << 8) | l;
+#else
+                s->mix.vol[8] = val;
+#endif
+                return put_user(s->mix.vol[8], (int *)arg);
+
+        case SOUND_MIXER_SPEAKER:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                l = val & 0xff;
+                if (l > 100)
+                        l = 100;
+                if(l < 3 ) {
+                        rl = 0;
+                        l = 0;
+                }
+                else {
+                        rl = (l*2 - 5)/13;          // Convert 0-100 range to 0-15.
+                        l = (rl*13 +5)/2;
+                }
+
+                if (rl < 3){
+                       temp1 = 0x8000;
+                       rl     = 0;
+                }
+                else
+                       temp1 = 0;
+                rl = 15 - rl;                       // Convert volume to attenuation.
+                temp1 |= rl << 1;
+                cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1);
+
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+                s->mix.vol[6] = l << 8;
+#else
+                s->mix.vol[6] = val;
+#endif
+                return put_user(s->mix.vol[6], (int *)arg);
+
+        case SOUND_MIXER_RECLEV:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                l = val & 0xff;
+                if (l > 100)
+                        l = 100;
+                r = (val >> 8) & 0xff;
+                if (r > 100)
+                        r = 100;
+                rl = (l*2 - 5) / 13;                // Convert 0-100 scale to 0-15.
+                rr = (r*2 - 5) / 13;
+                if (rl <3 && rr <3)
+                        temp1 = 0x8000;
+                else
+                        temp1 = 0;
+
+                temp1 = temp1 | (rl << 8) | rr;
+                cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1); 
+
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+                s->mix.vol[7] = ((unsigned int)r << 8) | l;
+#else
+                s->mix.vol[7] = val;
+#endif
+                return put_user(s->mix.vol[7], (int *)arg);
+
+        case SOUND_MIXER_MIC:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                l = val & 0xff;
+                if (l > 100)
+                        l = 100;
+                if (l < 1) {
+                        l = 0;
+                        rl = 0;
+                }
+                else {
+                        rl = ((unsigned)l*5 - 4)/16; // Convert 0-100 range to 0-31.
+                        l  = (rl*16 +4)/5;
+                }
+                cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
+                temp1 &= 0x40;                      // Isolate 20db gain bit.
+                if (rl < 3){
+                       temp1 |= 0x8000;
+                       rl     = 0;
+                }
+                rl = 31 - rl;                       // Convert volume to attenuation.
+                temp1 |= rl; 
+                cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
+
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+                s->mix.vol[5] = val << 8;
+#else
+                s->mix.vol[5] = val;
+#endif
+                return put_user(s->mix.vol[5], (int *)arg);
+        
+        
+        case SOUND_MIXER_SYNTH:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                l = val & 0xff;
+                if (l > 100)
+                        l = 100;
+                get_user_ret(val, (int *)arg, -EFAULT);
+                r = (val >> 8) & 0xff;
+                if (r > 100)
+                        r = 100;
+                rl = (l * 2 - 11)/3;        // Convert 0-100 range to 0-63.
+                rr = (r * 2 - 11)/3;
+                if (rl < 3)                 // If l is low, turn on
+                        temp1 = 0x0080;     //  the mute bit.
+                else
+                        temp1 = 0;
+
+                rl = 63 - rl;               // Convert vol to attenuation.
+                writel(temp1|rl, s->pBA0+BA0_FMLVC);
+                if (rr < 3)                 //  If rr is low, turn on
+                        temp1 = 0x0080;     //   the mute bit.
+                else
+                        temp1 = 0;
+                rr = 63 - rr;               // Convert vol to attenuation.
+                writel(temp1 | rr, s->pBA0+BA0_FMRVC);
+
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+                s->mix.vol[4] = (r << 8) | l;
+#else
+                s->mix.vol[4] = val;
+#endif
+                return put_user(s->mix.vol[4], (int *)arg);
+
+                
+        default:
+                i = _IOC_NR(cmd);
+                if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
+                        return -EINVAL;
+                get_user_ret(val, (int *)arg, -EFAULT);
+                l = val & 0xff;
+                if (l > 100)
+                        l = 100;
+                if (l < 1) {
+                        l = 0;
+                        rl = 31;
+                }
+                else 
+                        rl = (attentbl[(l*10)/100])>>1;
+                
+                r = (val >> 8) & 0xff;
+                if (r > 100)
+                        r = 100;
+                if (r < 1) {
+                        r = 0;
+                        rr = 31;
+                }
+                else 
+                        rr = (attentbl[(r*10)/100])>>1;                        
+                if ((rl > 30) && (rr > 30))
+                        temp1 = 0x8000;
+                else
+                        temp1 = 0;
+                temp1 = temp1 | (rl << 8) | rr;              
+                cs4281_write_ac97(s, mixreg[vidx-1], temp1);
+                
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+                s->mix.vol[vidx-1] = ((unsigned int)r << 8) | l;
+#else
+                s->mix.vol[vidx-1] = val;
+#endif
+                return put_user(s->mix.vol[vidx-1], (int *)arg);
+        }
+}
+
+
+// --------------------------------------------------------------------- 
+
+static loff_t cs4281_llseek(struct file *file, loff_t offset, int origin)
+{
+        return -ESPIPE;
+}
+
+
+// --------------------------------------------------------------------- 
+
+static int cs4281_open_mixdev(struct inode *inode, struct file *file)
+{
+        int minor = MINOR(inode->i_rdev);
+        struct cs4281_state *s = devs;
+
+        while (s && s->dev_mixer != minor)
+                s = s->next;
+        if (!s)
+                return -ENODEV;
+        VALIDATE_STATE(s);
+        file->private_data = s;
+        MOD_INC_USE_COUNT;
+        return 0;
+}
+
+
+static int cs4281_release_mixdev(struct inode *inode, struct file *file)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+
+        VALIDATE_STATE(s);
+        MOD_DEC_USE_COUNT;
+        return 0;
+}
+
+
+static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file,
+                               unsigned int cmd, unsigned long arg)
+{
+        return mixer_ioctl((struct cs4281_state *)file->private_data, cmd, arg);
+}
+
+
+// ******************************************************************************************
+//   Mixer file operations struct.
+// ******************************************************************************************
+static /*const*/ struct file_operations cs4281_mixer_fops = {
+        &cs4281_llseek,
+        NULL,  // read 
+        NULL,  // write 
+        NULL,  // readdir 
+        NULL,  // poll 
+        &cs4281_ioctl_mixdev,
+        NULL,  // mmap 
+        &cs4281_open_mixdev,
+        NULL,  // flush 
+        &cs4281_release_mixdev,
+        NULL,  // fsync 
+        NULL,  // fasync 
+        NULL,  // check_media_change 
+        NULL,  // revalidate 
+        NULL,  // lock 
+};
+
+
+// --------------------------------------------------------------------- 
+
+static int drain_dac(struct cs4281_state *s, int nonblock)
+{
+        DECLARE_WAITQUEUE(wait, current);
+        unsigned long flags;
+        int count;
+        unsigned tmo;
+
+        if (s->dma_dac.mapped)
+                return 0;
+        current->state = TASK_INTERRUPTIBLE;
+        add_wait_queue(&s->dma_dac.wait, &wait);
+        for (;;) {
+                spin_lock_irqsave(&s->lock, flags);
+                count = s->dma_dac.count;
+                spin_unlock_irqrestore(&s->lock, flags);
+                if (count <= 0)
+                        break;
+                if (signal_pending(current))
+                        break;
+                if (nonblock) {
+                        remove_wait_queue(&s->dma_dac.wait, &wait);
+                        current->state = TASK_RUNNING;
+                        return -EBUSY;
+                }
+                tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->rate;
+                if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
+                        tmo >>= 1;
+                if (s->channels > 1)
+                        tmo >>= 1;
+                if (!schedule_timeout(tmo + 1))
+                        printk(KERN_DEBUG "cs4281: dma timed out??\n");
+        }
+        remove_wait_queue(&s->dma_dac.wait, &wait);
+        current->state = TASK_RUNNING;
+        if (signal_pending(current))
+                return -ERESTARTSYS;
+        return 0;
+}
+
+
+// --------------------------------------------------------------------- 
+
+static ssize_t cs4281_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        ssize_t ret;
+        unsigned long flags;
+        unsigned swptr;
+        int cnt;
+
+        VALIDATE_STATE(s);
+        if (ppos != &file->f_pos)
+                return -ESPIPE;
+        if (s->dma_adc.mapped)
+                return -ENXIO;
+        if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
+                return ret;
+        if (!access_ok(VERIFY_WRITE, buffer, count))
+                return -EFAULT;
+        ret = 0;
+        while (count > 0) {
+                spin_lock_irqsave(&s->lock, flags);
+                swptr = s->dma_adc.swptr;
+                cnt = s->dma_adc.dmasize-swptr;
+                if (s->dma_adc.count < cnt)
+                        cnt = s->dma_adc.count;
+                spin_unlock_irqrestore(&s->lock, flags);
+                if (cnt > count)
+                        cnt = count;
+                if (cnt <= 0) {
+                        start_adc(s);
+                         if (file->f_flags & O_NONBLOCK)
+                                return ret ? ret : -EAGAIN;
+                        interruptible_sleep_on(&s->dma_adc.wait);
+                        if (signal_pending(current))
+                                return ret ? ret : -ERESTARTSYS;
+                        continue;
+                }
+                if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt))
+                        return ret ? ret : -EFAULT;
+                swptr = (swptr + cnt) % s->dma_adc.dmasize;
+                spin_lock_irqsave(&s->lock, flags);
+                s->dma_adc.swptr = swptr;
+                s->dma_adc.count -= cnt;
+                spin_unlock_irqrestore(&s->lock, flags);
+                count -= cnt;
+                buffer += cnt;
+                ret += cnt;
+                start_adc(s);
+        }
+        return ret;
+}
+
+
+static ssize_t cs4281_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        ssize_t ret;
+        unsigned long flags;
+        unsigned swptr;
+        int cnt;
+
+        VALIDATE_STATE(s);
+
+        if (ppos != &file->f_pos)
+                return -ESPIPE;
+        if (s->dma_dac.mapped)
+                return -ENXIO;
+        if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
+                return ret;
+        if (!access_ok(VERIFY_READ, buffer, count))
+                return -EFAULT;
+        ret = 0;
+        while (count > 0) {
+                spin_lock_irqsave(&s->lock, flags);
+                if (s->dma_dac.count < 0) {
+                        s->dma_dac.count = 0;
+                        s->dma_dac.swptr = s->dma_dac.hwptr;
+                }
+                swptr = s->dma_dac.swptr;
+                cnt = s->dma_dac.dmasize-swptr;
+                if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
+                        cnt = s->dma_dac.dmasize - s->dma_dac.count;
+                spin_unlock_irqrestore(&s->lock, flags);
+                if (cnt > count)
+                        cnt = count;
+                if (cnt <= 0) {
+                        start_dac(s);
+                        if (file->f_flags & O_NONBLOCK)
+                                return ret ? ret : -EAGAIN;
+                        interruptible_sleep_on(&s->dma_dac.wait);
+                        if (signal_pending(current))
+                                return ret ? ret : -ERESTARTSYS;
+                        continue;
+                }
+                if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt))
+                        return ret ? ret : -EFAULT;
+                swptr = (swptr + cnt) % s->dma_dac.dmasize;
+                spin_lock_irqsave(&s->lock, flags);
+                s->dma_dac.swptr = swptr;
+                s->dma_dac.count += cnt;
+                s->dma_dac.endcleared = 0;
+                spin_unlock_irqrestore(&s->lock, flags);
+                count -= cnt;
+                buffer += cnt;
+                ret += cnt;
+                start_dac(s);
+        }
+        return ret;
+}
+
+
+static unsigned int cs4281_poll(struct file *file, struct poll_table_struct *wait)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        unsigned long flags;
+        unsigned int mask = 0;
+
+        VALIDATE_STATE(s);
+        if (file->f_mode & FMODE_WRITE)
+                poll_wait(file, &s->dma_dac.wait, wait);
+        if (file->f_mode & FMODE_READ)
+                poll_wait(file, &s->dma_adc.wait, wait);
+        spin_lock_irqsave(&s->lock, flags);
+        cs4281_update_ptr(s);
+        if (file->f_mode & FMODE_READ) {
+                if (s->dma_adc.mapped) {
+                        if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
+                                mask |= POLLIN | POLLRDNORM;
+                } else {
+                        if (s->dma_adc.count > 0)
+                                mask |= POLLIN | POLLRDNORM;
+                }
+        }
+        if (file->f_mode & FMODE_WRITE) {
+                if (s->dma_dac.mapped) {
+                        if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
+                                mask |= POLLOUT | POLLWRNORM;
+                } else {
+                        if ((signed)s->dma_dac.dmasize > s->dma_dac.count)
+                                mask |= POLLOUT | POLLWRNORM;
+                }
+        }
+        spin_unlock_irqrestore(&s->lock, flags);
+        return mask;
+}
+
+
+static int cs4281_mmap(struct file *file, struct vm_area_struct *vma)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        struct dmabuf *db;
+        int ret;
+        unsigned long size;
+
+        VALIDATE_STATE(s);
+        if (vma->vm_flags & VM_WRITE) {
+                if ((ret = prog_dmabuf_dac(s)) != 0)
+                        return ret;
+                db = &s->dma_dac;
+        } else if (vma->vm_flags & VM_READ) {
+                if ((ret = prog_dmabuf_adc(s)) != 0)
+                        return ret;
+                db = &s->dma_adc;
+        } else
+                return -EINVAL;
+        if (vma->vm_offset != 0)
+                return -EINVAL;
+        size = vma->vm_end - vma->vm_start;
+        if (size > (PAGE_SIZE << db->buforder))
+                return -EINVAL;
+        if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
+                return -EAGAIN;
+        db->mapped = 1;
+        return 0;
+}
+
+
+static int cs4281_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        unsigned long flags;
+        audio_buf_info abinfo;
+        count_info cinfo;
+        int val, mapped, ret;
+  
+        VALIDATE_STATE(s);
+        mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
+                ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
+        switch (cmd) {
+        case OSS_GETVERSION:
+                return put_user(SOUND_VERSION, (int *)arg);
+
+        case SNDCTL_DSP_SYNC:
+                if (file->f_mode & FMODE_WRITE)
+                        return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
+                return 0;
+
+        case SNDCTL_DSP_SETDUPLEX:
+                return 0;
+
+        case SNDCTL_DSP_GETCAPS:
+                return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
+
+        case SNDCTL_DSP_RESET:
+                if (file->f_mode & FMODE_WRITE) {
+                        stop_dac(s);
+                        synchronize_irq();
+                        s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
+                }
+                if (file->f_mode & FMODE_READ) {
+                        stop_adc(s);
+                        synchronize_irq();
+                        s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
+                }
+                prog_codec(s);
+                return 0;
+
+        case SNDCTL_DSP_SPEED:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                if (val >= 0) {
+                        stop_adc(s);
+                        stop_dac(s);
+                        s->dma_adc.ready = s->dma_dac.ready = 0;
+                        // program sampling rates 
+                        if (val > 48000)
+                                val = 48000;
+                        if (val < 6300)
+                                val = 6300;
+                        s->rate = val;
+                        prog_codec(s);
+                }
+                return put_user(s->rate, (int *)arg);
+
+        case SNDCTL_DSP_STEREO:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                stop_adc(s);
+                stop_dac(s);
+                s->dma_adc.ready = s->dma_dac.ready = 0;
+                // program channels 
+                s->channels = val ? 2 : 1;
+                prog_codec(s);
+                return 0;
+
+        case SNDCTL_DSP_CHANNELS:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                if (val != 0) {
+                        stop_adc(s);
+                        stop_dac(s);
+                        s->dma_adc.ready = s->dma_dac.ready = 0;
+                        // program channels 
+                        s->channels = val ? 2 : 1;
+                        prog_codec(s);
+                }
+                return put_user(s->channels, (int *)arg);
+
+        case SNDCTL_DSP_GETFMTS: // Returns a mask 
+                return put_user(AFMT_S16_LE|AFMT_U16_LE|AFMT_S8|AFMT_U8, (int *)arg);
+
+        case SNDCTL_DSP_SETFMT: // Selects ONE fmt
+                get_user_ret(val, (int *)arg, -EFAULT);
+                if (val != AFMT_QUERY) {
+                        stop_adc(s);
+                        stop_dac(s);
+                        s->dma_adc.ready = s->dma_dac.ready = 0;
+                        // program format 
+                        if (val != AFMT_S16_LE && val != AFMT_U16_LE &&
+                            val != AFMT_S8 && val != AFMT_U8)
+                                val = AFMT_U8;
+                        s->fmt = val;
+                        prog_codec(s);
+                }
+                return put_user(s->fmt, (int *)arg);
+
+        case SNDCTL_DSP_POST:
+                return 0;
+
+        case SNDCTL_DSP_GETTRIGGER:
+                val = 0;
+                if (file->f_mode & s->ena & FMODE_READ)
+                        val |= PCM_ENABLE_INPUT;
+                if (file->f_mode & s->ena & FMODE_WRITE)
+                        val |= PCM_ENABLE_OUTPUT;
+                return put_user(val, (int *)arg);
+
+        case SNDCTL_DSP_SETTRIGGER:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                if (file->f_mode & FMODE_READ) {
+                        if (val & PCM_ENABLE_INPUT) {
+                                if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
+                                        return ret;
+                                start_adc(s);
+                        } else
+                                stop_adc(s);
+                }
+                if (file->f_mode & FMODE_WRITE) {
+                        if (val & PCM_ENABLE_OUTPUT) {
+                                if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
+                                        return ret;
+                                start_dac(s);
+                        } else
+                                stop_dac(s);
+                }
+                return 0;
+
+        case SNDCTL_DSP_GETOSPACE:
+                if (!(file->f_mode & FMODE_WRITE))
+                        return -EINVAL;
+                if (!(s->ena & FMODE_WRITE) && (val = prog_dmabuf_dac(s)) != 0)
+                        return val;
+                spin_lock_irqsave(&s->lock, flags);
+                cs4281_update_ptr(s);
+                abinfo.fragsize = s->dma_dac.fragsize;
+                abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
+                abinfo.fragstotal = s->dma_dac.numfrag;
+                abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;  
+                spin_unlock_irqrestore(&s->lock, flags);
+                return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
+
+        case SNDCTL_DSP_GETISPACE:
+                if (!(file->f_mode & FMODE_READ))
+                        return -EINVAL;
+                if (!(s->ena & FMODE_READ) && (val = prog_dmabuf_adc(s)) != 0)
+                        return val;
+                spin_lock_irqsave(&s->lock, flags);
+                cs4281_update_ptr(s);
+                abinfo.fragsize = s->dma_adc.fragsize;
+                abinfo.bytes = s->dma_adc.count;
+                abinfo.fragstotal = s->dma_adc.numfrag;
+                abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
+                spin_unlock_irqrestore(&s->lock, flags);
+                return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
+
+        case SNDCTL_DSP_NONBLOCK:
+                file->f_flags |= O_NONBLOCK;
+                return 0;
+
+        case SNDCTL_DSP_GETODELAY:
+                if (!(file->f_mode & FMODE_WRITE))
+                        return -EINVAL;
+                spin_lock_irqsave(&s->lock, flags);
+                cs4281_update_ptr(s);
+                val = s->dma_dac.count;
+                spin_unlock_irqrestore(&s->lock, flags);
+                return put_user(val, (int *)arg);
+
+        case SNDCTL_DSP_GETIPTR:
+                if (!(file->f_mode & FMODE_READ))
+                        return -EINVAL;
+                spin_lock_irqsave(&s->lock, flags);
+                cs4281_update_ptr(s);
+                cinfo.bytes = s->dma_adc.total_bytes;
+                cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
+                cinfo.ptr = s->dma_adc.hwptr;
+                if (s->dma_adc.mapped)
+                        s->dma_adc.count &= s->dma_adc.fragsize-1;
+                spin_unlock_irqrestore(&s->lock, flags);
+                return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
+
+        case SNDCTL_DSP_GETOPTR:
+                if (!(file->f_mode & FMODE_WRITE))
+                        return -EINVAL;
+                spin_lock_irqsave(&s->lock, flags);
+                cs4281_update_ptr(s);
+                cinfo.bytes = s->dma_dac.total_bytes;
+                cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
+                cinfo.ptr = s->dma_dac.hwptr;
+                if (s->dma_dac.mapped)
+                        s->dma_dac.count &= s->dma_dac.fragsize-1;
+                spin_unlock_irqrestore(&s->lock, flags);
+                return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
+
+        case SNDCTL_DSP_GETBLKSIZE:
+                if (file->f_mode & FMODE_WRITE) {
+                        if ((val = prog_dmabuf_dac(s)))
+                                return val;
+                        return put_user(s->dma_dac.fragsize, (int *)arg);
+                }
+                if ((val = prog_dmabuf_adc(s)))
+                        return val;
+                return put_user(s->dma_adc.fragsize, (int *)arg);
+
+        case SNDCTL_DSP_SETFRAGMENT:
+                get_user_ret(val, (int *)arg, -EFAULT);
+                return 0;              // Say OK, but do nothing.
+
+        case SNDCTL_DSP_SUBDIVIDE:
+                if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
+                    (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
+                        return -EINVAL;
+                get_user_ret(val, (int *)arg, -EFAULT);
+                if (val != 1 && val != 2 && val != 4)
+                        return -EINVAL;
+                if (file->f_mode & FMODE_READ)
+                        s->dma_adc.subdivision = val;
+                if (file->f_mode & FMODE_WRITE)
+                        s->dma_dac.subdivision = val;
+                return 0;
+
+        case SOUND_PCM_READ_RATE:
+                return put_user(s->rate, (int *)arg);
+
+        case SOUND_PCM_READ_CHANNELS:
+                return put_user(s->channels, (int *)arg);
+
+        case SOUND_PCM_READ_BITS:
+                return put_user((s->fmt & (AFMT_S8|AFMT_U8)) ? 8 : 16, (int *)arg);
+
+        case SOUND_PCM_WRITE_FILTER:
+        case SNDCTL_DSP_SETSYNCRO:
+        case SOUND_PCM_READ_FILTER:
+                return -EINVAL;
+
+        }
+        return mixer_ioctl(s, cmd, arg);
+}
+
+
+static int cs4281_release(struct inode *inode, struct file *file)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+
+        VALIDATE_STATE(s);
+
+        if (file->f_mode & FMODE_WRITE)
+                drain_dac(s, file->f_flags & O_NONBLOCK);
+        down(&s->open_sem);
+        if (file->f_mode & FMODE_WRITE) {
+                stop_dac(s);
+                dealloc_dmabuf(&s->dma_dac);
+        }
+        if (file->f_mode & FMODE_READ) {
+                stop_adc(s);
+                dealloc_dmabuf(&s->dma_adc);
+        }
+        s->open_mode &= ~(FMODE_READ | FMODE_WRITE);
+        up(&s->open_sem);
+        wake_up(&s->open_wait);
+        MOD_DEC_USE_COUNT;
+        return 0;
+}
+
+static int cs4281_open(struct inode *inode, struct file *file)
+{
+        int minor = MINOR(inode->i_rdev);
+        struct cs4281_state *s = devs;
+
+        while (s && ((s->dev_audio ^ minor) & ~0xf))
+                s = s->next;
+        if (!s)
+                return -ENODEV;
+        VALIDATE_STATE(s);
+        file->private_data = s;
+        
+                // wait for device to become free 
+        down(&s->open_sem);
+        while (s->open_mode & (FMODE_READ | FMODE_WRITE)) {
+                if (file->f_flags & O_NONBLOCK) {
+                        up(&s->open_sem);
+                        return -EBUSY;
+                }
+                up(&s->open_sem);
+                interruptible_sleep_on(&s->open_wait);
+                if (signal_pending(current))
+                        return -ERESTARTSYS;
+                down(&s->open_sem);
+        }
+        s->fmt = AFMT_U8;
+        s->channels = 1;
+        s->rate = 8000;
+        s->clkdiv = 96 | 0x80;
+        s->ena = 0;
+	s->endofbuffer = 0;
+        s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
+        s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
+        s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
+        up(&s->open_sem);
+        MOD_INC_USE_COUNT;
+
+        if (prog_dmabuf_dac(s) || prog_dmabuf_adc(s)) {
+                
+             printk(KERN_ERR "cs4281: Program dmabufs failed.\n");
+             cs4281_release(inode, file);
+                
+             return -ENOMEM;
+        }
+        prog_codec(s);
+        return 0;
+}
+
+
+// ******************************************************************************************
+//   Wave (audio) file operations struct.
+// ******************************************************************************************
+static /*const*/ struct file_operations cs4281_audio_fops = {
+        &cs4281_llseek,
+        &cs4281_read,
+        &cs4281_write,
+        NULL,  // readdir 
+        &cs4281_poll,
+        &cs4281_ioctl,
+        &cs4281_mmap,
+        &cs4281_open,
+        NULL,  // flush 
+        &cs4281_release,
+        NULL,  // fsync 
+        NULL,  // fasync 
+        NULL,  // check_media_change 
+        NULL,  // revalidate 
+        NULL,  // lock 
+};
+
+// --------------------------------------------------------------------- 
+
+// hold spinlock for the following! 
+static void cs4281_handle_midi(struct cs4281_state *s)
+{
+        unsigned char ch;
+        int wake;
+        unsigned temp1;
+
+        wake = 0;
+        while (!(readl(s->pBA0+ BA0_MIDSR) & 0x80)) {
+                ch = readl(s->pBA0+BA0_MIDRP);
+                if (s->midi.icnt < MIDIINBUF) {
+                        s->midi.ibuf[s->midi.iwr] = ch;
+                        s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
+                        s->midi.icnt++;
+                }
+                wake = 1;
+        }
+        if (wake)
+                wake_up(&s->midi.iwait);
+        wake = 0;
+        while (!(readl(s->pBA0+ BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) {
+                temp1 = ( s->midi.obuf[s->midi.ord] ) & 0x000000ff;
+                writel(temp1, s->pBA0+BA0_MIDWP);
+                s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
+                s->midi.ocnt--;
+                if (s->midi.ocnt < MIDIOUTBUF-16)
+                        wake = 1;
+        }
+        if (wake)
+                wake_up(&s->midi.owait);
+}
+
+
+
+static void cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        struct cs4281_state *s = (struct cs4281_state *)dev_id;
+        unsigned int temp1;
+
+        // fastpath out, to ease interrupt sharing 
+        temp1 = readl(s->pBA0+BA0_HISR);                          // Get Int Status reg.
+        if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) {     // If not DMA or MIDI int,
+                writel(HICR_IEV| HICR_CHGM, s->pBA0+BA0_HICR);    //  reenable interrupts
+                return;                                           //   and return.
+        }
+        
+        if(temp1 & HISR_DMA0)                      // If play interrupt,
+                readl(s->pBA0+BA0_HDSR0);              //   clear the source.
+
+        if(temp1 & HISR_DMA1)                      // Same for play.
+                readl(s->pBA0+BA0_HDSR1);        
+        writel(HICR_IEV| HICR_CHGM, s->pBA0+BA0_HICR);  // Local EOI
+        
+        spin_lock(&s->lock);
+	//
+	// ok, at this point we assume that the fifos have been filled
+	// with silence and so we now turn off the DMA engine.
+	// if FMODE_WRITE is set that means that some thread
+	// attempted to start_dac, which probably means that an open
+	// occurred, so do not stop the dac in this case.
+	//
+	if(s->endofbuffer && !(s->ena & FMODE_WRITE))
+	{
+		writel(temp1|DCRn_MSK, s->pBA0+BA0_DCR0);    // Stop Play DMA
+		s->endofbuffer = 0;
+	}
+	else
+	{
+        	cs4281_update_ptr(s);
+	}
+        cs4281_handle_midi(s);
+        spin_unlock(&s->lock);
+}
+
+// **************************************************************************
+
+static void cs4281_midi_timer(unsigned long data)
+{
+        struct cs4281_state *s = (struct cs4281_state *)data;
+        unsigned long flags;
+
+        spin_lock_irqsave(&s->lock, flags);
+        cs4281_handle_midi(s);
+        spin_unlock_irqrestore(&s->lock, flags);
+        s->midi.timer.expires = jiffies+1;
+        add_timer(&s->midi.timer);
+}
+
+
+// --------------------------------------------------------------------- 
+
+static ssize_t cs4281_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        ssize_t ret;
+        unsigned long flags;
+        unsigned ptr;
+        int cnt;
+
+        VALIDATE_STATE(s);
+        if (ppos != &file->f_pos)
+                return -ESPIPE;
+        if (!access_ok(VERIFY_WRITE, buffer, count))
+                return -EFAULT;
+        ret = 0;
+        while (count > 0) {
+                spin_lock_irqsave(&s->lock, flags);
+                ptr = s->midi.ird;
+                cnt = MIDIINBUF - ptr;
+                if (s->midi.icnt < cnt)
+                        cnt = s->midi.icnt;
+                spin_unlock_irqrestore(&s->lock, flags);
+                if (cnt > count)
+                        cnt = count;
+                if (cnt <= 0) {
+                        if (file->f_flags & O_NONBLOCK)
+                                return ret ? ret : -EAGAIN;
+                        interruptible_sleep_on(&s->midi.iwait);
+                        if (signal_pending(current))
+                                return ret ? ret : -ERESTARTSYS;
+                        continue;
+                }
+                if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt))
+                        return ret ? ret : -EFAULT;
+                ptr = (ptr + cnt) % MIDIINBUF;
+                spin_lock_irqsave(&s->lock, flags);
+                s->midi.ird = ptr;
+                s->midi.icnt -= cnt;
+                spin_unlock_irqrestore(&s->lock, flags);
+                count -= cnt;
+                buffer += cnt;
+                ret += cnt;
+        }
+        return ret;
+}
+
+
+static ssize_t cs4281_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        ssize_t ret;
+        unsigned long flags;
+        unsigned ptr;
+        int cnt;
+
+        VALIDATE_STATE(s);
+        if (ppos != &file->f_pos)
+                return -ESPIPE;
+        if (!access_ok(VERIFY_READ, buffer, count))
+                return -EFAULT;
+        ret = 0;
+        while (count > 0) {
+                spin_lock_irqsave(&s->lock, flags);
+                ptr = s->midi.owr;
+                cnt = MIDIOUTBUF - ptr;
+                if (s->midi.ocnt + cnt > MIDIOUTBUF)
+                        cnt = MIDIOUTBUF - s->midi.ocnt;
+                if (cnt <= 0)
+                        cs4281_handle_midi(s);
+                spin_unlock_irqrestore(&s->lock, flags);
+                if (cnt > count)
+                        cnt = count;
+                if (cnt <= 0) {
+                        if (file->f_flags & O_NONBLOCK)
+                                return ret ? ret : -EAGAIN;
+                        interruptible_sleep_on(&s->midi.owait);
+                        if (signal_pending(current))
+                                return ret ? ret : -ERESTARTSYS;
+                        continue;
+                }
+                if (copy_from_user(s->midi.obuf + ptr, buffer, cnt))
+                        return ret ? ret : -EFAULT;
+                ptr = (ptr + cnt) % MIDIOUTBUF;
+                spin_lock_irqsave(&s->lock, flags);
+                s->midi.owr = ptr;
+                s->midi.ocnt += cnt;
+                spin_unlock_irqrestore(&s->lock, flags);
+                count -= cnt;
+                buffer += cnt;
+                ret += cnt;
+                spin_lock_irqsave(&s->lock, flags);
+                cs4281_handle_midi(s);
+                spin_unlock_irqrestore(&s->lock, flags);
+        }
+        return ret;
+}
+
+
+static unsigned int cs4281_midi_poll(struct file *file, struct poll_table_struct *wait)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        unsigned long flags;
+        unsigned int mask = 0;
+
+        VALIDATE_STATE(s);
+        if (file->f_flags & FMODE_WRITE)
+                poll_wait(file, &s->midi.owait, wait);
+        if (file->f_flags & FMODE_READ)
+                poll_wait(file, &s->midi.iwait, wait);
+        spin_lock_irqsave(&s->lock, flags);
+        if (file->f_flags & FMODE_READ) {
+                if (s->midi.icnt > 0)
+                        mask |= POLLIN | POLLRDNORM;
+        }
+        if (file->f_flags & FMODE_WRITE) {
+                if (s->midi.ocnt < MIDIOUTBUF)
+                        mask |= POLLOUT | POLLWRNORM;
+        }
+        spin_unlock_irqrestore(&s->lock, flags);
+        return mask;
+}
+
+
+static int cs4281_midi_open(struct inode *inode, struct file *file)
+{
+        int minor = MINOR(inode->i_rdev);
+        struct cs4281_state *s = devs;
+        unsigned long flags,temp1;
+        while (s && s->dev_midi != minor)
+                s = s->next;
+        if (!s)
+                return -ENODEV;
+        VALIDATE_STATE(s);
+        file->private_data = s;
+        // wait for device to become free 
+        down(&s->open_sem);
+        while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
+                if (file->f_flags & O_NONBLOCK) {
+                        up(&s->open_sem);
+                        return -EBUSY;
+                }
+                up(&s->open_sem);
+                interruptible_sleep_on(&s->open_wait);
+                if (signal_pending(current))
+                        return -ERESTARTSYS;
+                down(&s->open_sem);
+        }
+        spin_lock_irqsave(&s->lock, flags);
+        if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
+                s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
+                s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
+                writel(1, s->pBA0+BA0_MIDCR);   // Reset the interface.
+                writel(0, s->pBA0+BA0_MIDCR);   // Return to normal mode.
+                s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
+                writel(0x0000000f, s->pBA0+BA0_MIDCR);                // Enable transmit, record, ints.
+                temp1 = readl(s->pBA0+BA0_HIMR);
+                writel(temp1 & 0xffbfffff, s->pBA0+BA0_HIMR);         // Enable midi int. recognition.
+                writel(HICR_IEV | HICR_CHGM, s->pBA0+BA0_HICR);       // Enable interrupts
+                init_timer(&s->midi.timer);
+                s->midi.timer.expires = jiffies+1;
+                s->midi.timer.data = (unsigned long)s;
+                s->midi.timer.function = cs4281_midi_timer;
+                add_timer(&s->midi.timer);
+        }
+        if (file->f_mode & FMODE_READ) {
+                s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
+        }
+        if (file->f_mode & FMODE_WRITE) {
+                s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
+        }
+        spin_unlock_irqrestore(&s->lock, flags);
+        s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
+        up(&s->open_sem);
+        MOD_INC_USE_COUNT;
+        return 0;
+}
+
+
+static int cs4281_midi_release(struct inode *inode, struct file *file)
+{
+        struct cs4281_state *s = (struct cs4281_state *)file->private_data;
+        DECLARE_WAITQUEUE(wait, current);
+        unsigned long flags;
+        unsigned count, tmo;
+
+        VALIDATE_STATE(s);
+
+        if (file->f_mode & FMODE_WRITE) {
+                current->state = TASK_INTERRUPTIBLE;
+                add_wait_queue(&s->midi.owait, &wait);
+                for (;;) {
+                        spin_lock_irqsave(&s->lock, flags);
+                        count = s->midi.ocnt;
+                        spin_unlock_irqrestore(&s->lock, flags);
+                        if (count <= 0)
+                                break;
+                        if (signal_pending(current))
+                                break;
+                        if (file->f_flags & O_NONBLOCK) {
+                                remove_wait_queue(&s->midi.owait, &wait);
+                                current->state = TASK_RUNNING;
+                                return -EBUSY;
+                        }
+                        tmo = (count * HZ) / 3100;
+                        if (!schedule_timeout(tmo ? : 1) && tmo)
+                                printk(KERN_DEBUG "cs4281: midi timed out??\n");
+                }
+                remove_wait_queue(&s->midi.owait, &wait);
+                current->state = TASK_RUNNING;
+        }
+        down(&s->open_sem);
+        s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
+        spin_lock_irqsave(&s->lock, flags);
+        if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
+                writel(0, s->pBA0+BA0_MIDCR);    // Disable Midi interrupts.  
+                del_timer(&s->midi.timer);
+        }
+        spin_unlock_irqrestore(&s->lock, flags);
+        up(&s->open_sem);
+        wake_up(&s->open_wait);
+        MOD_DEC_USE_COUNT;
+        return 0;
+}
+
+// ******************************************************************************************
+//   Midi file operations struct.
+// ******************************************************************************************
+static /*const*/ struct file_operations cs4281_midi_fops = {
+        &cs4281_llseek,
+        &cs4281_midi_read,
+        &cs4281_midi_write,
+        NULL,  // readdir 
+        &cs4281_midi_poll,
+        NULL,  // ioctl 
+        NULL,  // mmap 
+        &cs4281_midi_open,
+        NULL,  // flush 
+        &cs4281_midi_release,
+        NULL,  // fsync 
+        NULL,  // fasync 
+        NULL,  // check_media_change 
+        NULL,  // revalidate 
+        NULL,  // lock 
+};
+
+
+// --------------------------------------------------------------------- 
+
+// maximum number of devices 
+#define NR_DEVICE 8          // Only eight devices supported currently.
+
+// --------------------------------------------------------------------- 
+
+static struct initvol {
+        int mixch;
+        int vol;
+} initvol[] __initdata = {
+        { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
+        { SOUND_MIXER_WRITE_PCM, 0x4040 },
+        { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
+        { SOUND_MIXER_WRITE_CD, 0x4040 },
+        { SOUND_MIXER_WRITE_LINE, 0x4040 },
+        { SOUND_MIXER_WRITE_LINE1, 0x4040 },
+        { SOUND_MIXER_WRITE_RECLEV, 0x0000 },
+        { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
+        { SOUND_MIXER_WRITE_MIC, 0x0000 }
+};
+
+
+int __init cs4281_probe(void)
+{
+        struct cs4281_state *s;
+        struct pci_dev *pcidev = NULL;
+        mm_segment_t fs;
+        int i, val, index = 0;
+        unsigned int temp1, temp2;
+ 
+        if (!pci_present())   // No PCI bus in this machine! 
+                return -ENODEV;
+        printk(KERN_INFO "cs4281: version 0.9 time " __TIME__ " " __DATE__ "\n");
+        while (index < NR_DEVICE && 
+        	(pcidev = pci_find_device(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CRYSTAL_CS4281, pcidev)))
+        {   
+                if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) {
+                        printk(KERN_ERR "cs4281: no memory for state struct.\n");
+                        continue;
+                }
+
+                memset(s, 0, sizeof(struct cs4281_state));
+                init_waitqueue_head(&s->dma_adc.wait);
+                init_waitqueue_head(&s->dma_dac.wait);
+                init_waitqueue_head(&s->open_wait);
+                init_waitqueue_head(&s->midi.iwait);
+                init_waitqueue_head(&s->midi.owait);
+                init_MUTEX(&s->open_sem);
+                s->pBA0phys = pcidev->base_address[0]&PCI_BASE_ADDRESS_MEM_MASK;                  // Get physical addresses
+                s->pBA1phys = pcidev->base_address[1]&PCI_BASE_ADDRESS_MEM_MASK;                  //  of part.
+		s->pBA0 = ioremap_nocache(s->pBA0phys, 4096);		// Convert phys 
+		s->pBA1 = ioremap_nocache(s->pBA1phys, 65536);  	//  to linear. 
+                temp1 = readl(s->pBA0+ BA0_PCICFG00);
+                temp2 = readl(s->pBA0+ BA0_PCICFG04);
+                temp1 = cs4281_hw_init(s);
+                if(!temp1){
+                        printk(KERN_INFO "cs4281: Init4281() failed. Skipping part.\n");
+                        continue;
+                }	
+                s->magic = CS4281_MAGIC;
+		s->pcidev = pcidev;
+                s->irq = pcidev->irq;
+                if(request_irq(s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)){
+                        printk(KERN_ERR "cs4281: irq %u in use\n", s->irq);
+                        goto err_irq;
+                }
+                if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) < 0)
+                        goto err_dev1;
+                if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) < 0)
+                        goto err_dev2;
+                if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0)
+                        goto err_dev3;
+                                    
+                pci_set_master(pcidev);           // enable bus mastering 
+
+                fs = get_fs();
+                set_fs(KERNEL_DS);
+                val = SOUND_MASK_LINE;
+                mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
+                for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
+                        val = initvol[i].vol;
+                        mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
+                }
+                val = 1; // enable mic preamp 
+                mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long)&val);
+                set_fs(fs);
+                
+                // queue it for later freeing 
+                s->next = devs;
+                devs = s;
+                index++;
+                continue;
+
+        err_dev3:
+                unregister_sound_mixer(s->dev_mixer);
+        err_dev2:
+                unregister_sound_dsp(s->dev_audio);
+        err_dev1:
+                printk(KERN_ERR "cs4281: cannot register dsp device\n");
+                free_irq(s->irq, s);
+        err_irq:
+                kfree_s(s, sizeof(struct cs4281_state));
+        } // endwhile
+        if (!devs)
+                return -ENODEV;
+        return 0;
+} // init_cs4281
+
+
+// --------------------------------------------------------------------- 
+
+
+#ifdef MODULE
+
+MODULE_AUTHOR("gw boynton, wesb@crystal.cirrus.com");
+MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver");
+
+int init_module(void)
+{
+	return cs4281_probe();
+}
+
+void cleanup_module(void)
+{
+        struct cs4281_state *s;
+        while ((s = devs)) {
+                devs = devs->next;
+                // stop DMA controller 
+                synchronize_irq();
+                free_irq(s->irq, s);              
+                unregister_sound_dsp(s->dev_audio);
+                unregister_sound_mixer(s->dev_mixer);
+                unregister_sound_midi(s->dev_midi);
+                iounmap(s->pBA0);
+                iounmap(s->pBA1);
+                kfree_s(s, sizeof(struct cs4281_state));
+        }
+}
+
+// --------------------------------------------------------------------- 
+
+#endif
diff -urN linux-2.2.17-pre16/drivers/sound/cs4281_hwdefs.h linux/drivers/sound/cs4281_hwdefs.h
--- linux-2.2.17-pre16/drivers/sound/cs4281_hwdefs.h	Wed Dec 31 16:00:00 1969
+++ linux/drivers/sound/cs4281_hwdefs.h	Mon Dec  3 22:11:10 2001
@@ -0,0 +1,1234 @@
+//****************************************************************************
+//
+// HWDEFS.H - Definitions of the registers and data structures used by the
+//            CS4281
+//
+// Copyright (c) 1999 Crystal Semiconductor Corp.
+//
+//****************************************************************************
+
+#ifndef _H_HWDEFS
+#define _H_HWDEFS
+
+//****************************************************************************
+//
+// The following define the offsets of the registers located in the PCI
+// configuration space of the CS4281 part.
+//
+//****************************************************************************
+#define PCICONFIG_DEVID_VENID                   0x00000000L
+#define PCICONFIG_STATUS_COMMAND                0x00000004L
+#define PCICONFIG_CLASS_REVISION                0x00000008L
+#define PCICONFIG_LATENCY_TIMER                 0x0000000CL
+#define PCICONFIG_BA0                           0x00000010L
+#define PCICONFIG_BA1                           0x00000014L
+#define PCICONFIG_SUBSYSID_SUBSYSVENID          0x0000002CL
+#define PCICONFIG_INTERRUPT                     0x0000003CL
+
+//****************************************************************************
+//
+// The following define the offsets of the registers accessed via base address
+// register zero on the CS4281 part.
+//
+//****************************************************************************
+#define BA0_HISR                                0x00000000L
+#define BA0_HICR                                0x00000008L
+#define BA0_HIMR                                0x0000000CL
+#define BA0_IIER                                0x00000010L
+#define BA0_HDSR0                               0x000000F0L
+#define BA0_HDSR1                               0x000000F4L
+#define BA0_HDSR2                               0x000000F8L
+#define BA0_HDSR3                               0x000000FCL
+#define BA0_DCA0                                0x00000110L
+#define BA0_DCC0                                0x00000114L
+#define BA0_DBA0                                0x00000118L
+#define BA0_DBC0                                0x0000011CL
+#define BA0_DCA1                                0x00000120L
+#define BA0_DCC1                                0x00000124L
+#define BA0_DBA1                                0x00000128L
+#define BA0_DBC1                                0x0000012CL
+#define BA0_DCA2                                0x00000130L
+#define BA0_DCC2                                0x00000134L
+#define BA0_DBA2                                0x00000138L
+#define BA0_DBC2                                0x0000013CL
+#define BA0_DCA3                                0x00000140L
+#define BA0_DCC3                                0x00000144L
+#define BA0_DBA3                                0x00000148L
+#define BA0_DBC3                                0x0000014CL
+#define BA0_DMR0                                0x00000150L
+#define BA0_DCR0                                0x00000154L
+#define BA0_DMR1                                0x00000158L
+#define BA0_DCR1                                0x0000015CL
+#define BA0_DMR2                                0x00000160L
+#define BA0_DCR2                                0x00000164L
+#define BA0_DMR3                                0x00000168L
+#define BA0_DCR3                                0x0000016CL
+#define BA0_DLMR                                0x00000170L
+#define BA0_DLSR                                0x00000174L
+#define BA0_FCR0                                0x00000180L
+#define BA0_FCR1                                0x00000184L
+#define BA0_FCR2                                0x00000188L
+#define BA0_FCR3                                0x0000018CL
+#define BA0_FPDR0                               0x00000190L
+#define BA0_FPDR1                               0x00000194L
+#define BA0_FPDR2                               0x00000198L
+#define BA0_FPDR3                               0x0000019CL
+#define BA0_FCHS                                0x0000020CL
+#define BA0_FSIC0                               0x00000210L
+#define BA0_FSIC1                               0x00000214L
+#define BA0_FSIC2                               0x00000218L
+#define BA0_FSIC3                               0x0000021CL
+#define BA0_PCICFG00                            0x00000300L
+#define BA0_PCICFG04                            0x00000304L
+#define BA0_PCICFG08                            0x00000308L
+#define BA0_PCICFG0C                            0x0000030CL
+#define BA0_PCICFG10                            0x00000310L
+#define BA0_PCICFG14                            0x00000314L
+#define BA0_PCICFG18                            0x00000318L
+#define BA0_PCICFG1C                            0x0000031CL
+#define BA0_PCICFG20                            0x00000320L
+#define BA0_PCICFG24                            0x00000324L
+#define BA0_PCICFG28                            0x00000328L
+#define BA0_PCICFG2C                            0x0000032CL
+#define BA0_PCICFG30                            0x00000330L
+#define BA0_PCICFG34                            0x00000334L
+#define BA0_PCICFG38                            0x00000338L
+#define BA0_PCICFG3C                            0x0000033CL
+#define BA0_PCICFG40                            0x00000340L
+#define BA0_PMCS                                0x00000344L
+#define BA0_CWPR                                0x000003E0L
+#define BA0_EPPMC                               0x000003E4L
+#define BA0_GPIOR                               0x000003E8L
+#define BA0_SPMC                                0x000003ECL
+#define BA0_CFLR                                0x000003F0L
+#define BA0_IISR                                0x000003F4L
+#define BA0_TMS                                 0x000003F8L
+#define BA0_SSVID                               0x000003FCL
+#define BA0_CLKCR1                              0x00000400L
+#define BA0_FRR                                 0x00000410L
+#define BA0_SLT12O                              0x0000041CL
+#define BA0_SERMC                               0x00000420L
+#define BA0_SERC1                               0x00000428L
+#define BA0_SERC2                               0x0000042CL
+#define BA0_SLT12M                              0x0000045CL
+#define BA0_ACCTL                               0x00000460L
+#define BA0_ACSTS                               0x00000464L
+#define BA0_ACOSV                               0x00000468L
+#define BA0_ACCAD                               0x0000046CL
+#define BA0_ACCDA                               0x00000470L
+#define BA0_ACISV                               0x00000474L
+#define BA0_ACSAD                               0x00000478L
+#define BA0_ACSDA                               0x0000047CL
+#define BA0_JSPT                                0x00000480L
+#define BA0_JSCTL                               0x00000484L
+#define BA0_MIDCR                               0x00000490L
+#define BA0_MIDCMD                              0x00000494L
+#define BA0_MIDSR                               0x00000494L
+#define BA0_MIDWP                               0x00000498L
+#define BA0_MIDRP                               0x0000049CL
+#define BA0_AODSD1                              0x000004A8L
+#define BA0_AODSD2                              0x000004ACL
+#define BA0_CFGI                                0x000004B0L
+#define BA0_SLT12M2                             0x000004DCL
+#define BA0_ACSTS2                              0x000004E4L
+#define BA0_ACISV2                              0x000004F4L
+#define BA0_ACSAD2                              0x000004F8L
+#define BA0_ACSDA2                              0x000004FCL
+#define BA0_IOTGP                               0x00000500L
+#define BA0_IOTSB                               0x00000504L
+#define BA0_IOTFM                               0x00000508L
+#define BA0_IOTDMA                              0x0000050CL
+#define BA0_IOTAC0                              0x00000500L
+#define BA0_IOTAC1                              0x00000504L
+#define BA0_IOTAC2                              0x00000508L
+#define BA0_IOTAC3                              0x0000050CL
+#define BA0_IOTPCP                              0x0000052CL
+#define BA0_IOTCC                               0x00000530L
+#define BA0_IOTCR                               0x0000058CL
+#define BA0_PCPRR                               0x00000600L
+#define BA0_PCPGR                               0x00000604L
+#define BA0_PCPCR                               0x00000608L
+#define BA0_PCPCIEN                             0x00000608L
+#define BA0_SBMAR                               0x00000700L
+#define BA0_SBMDR                               0x00000704L
+#define BA0_SBRR                                0x00000708L
+#define BA0_SBRDP                               0x0000070CL
+#define BA0_SBWDP                               0x00000710L
+#define BA0_SBWBS                               0x00000710L
+#define BA0_SBRBS                               0x00000714L
+#define BA0_FMSR                                0x00000730L
+#define BA0_B0AP                                0x00000730L
+#define BA0_FMDP                                0x00000734L
+#define BA0_B1AP                                0x00000738L
+#define BA0_B1DP                                0x0000073CL
+#define BA0_SSPM                                0x00000740L
+#define BA0_DACSR                               0x00000744L
+#define BA0_ADCSR                               0x00000748L
+#define BA0_SSCR                                0x0000074CL
+#define BA0_FMLVC                               0x00000754L
+#define BA0_FMRVC                               0x00000758L
+#define BA0_SRCSA                               0x0000075CL
+#define BA0_PPLVC                               0x00000760L
+#define BA0_PPRVC                               0x00000764L
+#define BA0_PASR                                0x00000768L
+#define BA0_CASR                                0x0000076CL
+
+//****************************************************************************
+//
+// The following define the offsets of the AC97 shadow registers, which appear
+// as a virtual extension to the base address register zero memory range.
+//
+//****************************************************************************
+#define AC97_REG_OFFSET_MASK                    0x0000007EL
+#define AC97_CODEC_NUMBER_MASK                  0x00003000L
+
+#define BA0_AC97_RESET                          0x00001000L
+#define BA0_AC97_MASTER_VOLUME                  0x00001002L
+#define BA0_AC97_HEADPHONE_VOLUME               0x00001004L
+#define BA0_AC97_MASTER_VOLUME_MONO             0x00001006L
+#define BA0_AC97_MASTER_TONE                    0x00001008L
+#define BA0_AC97_PC_BEEP_VOLUME                 0x0000100AL
+#define BA0_AC97_PHONE_VOLUME                   0x0000100CL
+#define BA0_AC97_MIC_VOLUME                     0x0000100EL
+#define BA0_AC97_LINE_IN_VOLUME                 0x00001010L
+#define BA0_AC97_CD_VOLUME                      0x00001012L
+#define BA0_AC97_VIDEO_VOLUME                   0x00001014L
+#define BA0_AC97_AUX_VOLUME                     0x00001016L
+#define BA0_AC97_PCM_OUT_VOLUME                 0x00001018L
+#define BA0_AC97_RECORD_SELECT                  0x0000101AL
+#define BA0_AC97_RECORD_GAIN                    0x0000101CL
+#define BA0_AC97_RECORD_GAIN_MIC                0x0000101EL
+#define BA0_AC97_GENERAL_PURPOSE                0x00001020L
+#define BA0_AC97_3D_CONTROL                     0x00001022L
+#define BA0_AC97_MODEM_RATE                     0x00001024L
+#define BA0_AC97_POWERDOWN                      0x00001026L
+#define BA0_AC97_EXT_AUDIO_ID                   0x00001028L
+#define BA0_AC97_EXT_AUDIO_POWER                0x0000102AL
+#define BA0_AC97_PCM_FRONT_DAC_RATE             0x0000102CL
+#define BA0_AC97_PCM_SURR_DAC_RATE              0x0000102EL
+#define BA0_AC97_PCM_LFE_DAC_RATE               0x00001030L
+#define BA0_AC97_PCM_LR_ADC_RATE                0x00001032L
+#define BA0_AC97_MIC_ADC_RATE                   0x00001034L
+#define BA0_AC97_6CH_VOL_C_LFE                  0x00001036L
+#define BA0_AC97_6CH_VOL_SURROUND               0x00001038L
+#define BA0_AC97_RESERVED_3A                    0x0000103AL
+#define BA0_AC97_EXT_MODEM_ID                   0x0000103CL
+#define BA0_AC97_EXT_MODEM_POWER                0x0000103EL
+#define BA0_AC97_LINE1_CODEC_RATE               0x00001040L
+#define BA0_AC97_LINE2_CODEC_RATE               0x00001042L
+#define BA0_AC97_HANDSET_CODEC_RATE             0x00001044L
+#define BA0_AC97_LINE1_CODEC_LEVEL              0x00001046L
+#define BA0_AC97_LINE2_CODEC_LEVEL              0x00001048L
+#define BA0_AC97_HANDSET_CODEC_LEVEL            0x0000104AL
+#define BA0_AC97_GPIO_PIN_CONFIG                0x0000104CL
+#define BA0_AC97_GPIO_PIN_TYPE                  0x0000104EL
+#define BA0_AC97_GPIO_PIN_STICKY                0x00001050L
+#define BA0_AC97_GPIO_PIN_WAKEUP                0x00001052L
+#define BA0_AC97_GPIO_PIN_STATUS                0x00001054L
+#define BA0_AC97_MISC_MODEM_AFE_STAT            0x00001056L
+#define BA0_AC97_RESERVED_58                    0x00001058L
+#define BA0_AC97_CRYSTAL_REV_N_FAB_ID           0x0000105AL
+#define BA0_AC97_TEST_AND_MISC_CTRL             0x0000105CL
+#define BA0_AC97_AC_MODE                        0x0000105EL
+#define BA0_AC97_MISC_CRYSTAL_CONTROL           0x00001060L
+#define BA0_AC97_LINE1_HYPRID_CTRL              0x00001062L
+#define BA0_AC97_VENDOR_RESERVED_64             0x00001064L
+#define BA0_AC97_VENDOR_RESERVED_66             0x00001066L
+#define BA0_AC97_SPDIF_CONTROL                  0x00001068L
+#define BA0_AC97_VENDOR_RESERVED_6A             0x0000106AL
+#define BA0_AC97_VENDOR_RESERVED_6C             0x0000106CL
+#define BA0_AC97_VENDOR_RESERVED_6E             0x0000106EL
+#define BA0_AC97_VENDOR_RESERVED_70             0x00001070L
+#define BA0_AC97_VENDOR_RESERVED_72             0x00001072L
+#define BA0_AC97_VENDOR_RESERVED_74             0x00001074L
+#define BA0_AC97_CAL_ADDRESS                    0x00001076L
+#define BA0_AC97_CAL_DATA                       0x00001078L
+#define BA0_AC97_VENDOR_RESERVED_7A             0x0000107AL
+#define BA0_AC97_VENDOR_ID1                     0x0000107CL
+#define BA0_AC97_VENDOR_ID2                     0x0000107EL
+
+//****************************************************************************
+//
+// The following define the offsets of the registers and memories accessed via
+// base address register one on the CS4281 part.
+//
+//****************************************************************************
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PCI device ID/vendor ID
+// register.
+//
+//****************************************************************************
+#define PDV_VENID_MASK                          0x0000FFFFL
+#define PDV_DEVID_MASK                          0xFFFF0000L
+#define PDV_VENID_SHIFT                         0L
+#define PDV_DEVID_SHIFT                         16L
+#define VENID_CIRRUS_LOGIC                      0x1013L
+#define DEVID_CS4281                            0x6005L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PCI status and command
+// register.
+//
+//****************************************************************************
+#define PSC_IO_SPACE_ENABLE                     0x00000001L
+#define PSC_MEMORY_SPACE_ENABLE                 0x00000002L
+#define PSC_BUS_MASTER_ENABLE                   0x00000004L
+#define PSC_SPECIAL_CYCLES                      0x00000008L
+#define PSC_MWI_ENABLE                          0x00000010L
+#define PSC_VGA_PALETTE_SNOOP                   0x00000020L
+#define PSC_PARITY_RESPONSE                     0x00000040L
+#define PSC_WAIT_CONTROL                        0x00000080L
+#define PSC_SERR_ENABLE                         0x00000100L
+#define PSC_FAST_B2B_ENABLE                     0x00000200L
+#define PSC_UDF_MASK                            0x007F0000L
+#define PSC_FAST_B2B_CAPABLE                    0x00800000L
+#define PSC_PARITY_ERROR_DETECTED               0x01000000L
+#define PSC_DEVSEL_TIMING_MASK                  0x06000000L
+#define PSC_TARGET_ABORT_SIGNALLED              0x08000000L
+#define PSC_RECEIVED_TARGET_ABORT               0x10000000L
+#define PSC_RECEIVED_MASTER_ABORT               0x20000000L
+#define PSC_SIGNALLED_SERR                      0x40000000L
+#define PSC_DETECTED_PARITY_ERROR               0x80000000L
+#define PSC_UDF_SHIFT                           16L
+#define PSC_DEVSEL_TIMING_SHIFT                 25L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PCI class/revision ID
+// register.
+//
+//****************************************************************************
+#define PCR_REVID_MASK                          0x000000FFL
+#define PCR_INTERFACE_MASK                      0x0000FF00L
+#define PCR_SUBCLASS_MASK                       0x00FF0000L
+#define PCR_CLASS_MASK                          0xFF000000L
+#define PCR_REVID_SHIFT                         0L
+#define PCR_INTERFACE_SHIFT                     8L
+#define PCR_SUBCLASS_SHIFT                      16L
+#define PCR_CLASS_SHIFT                         24L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PCI latency timer register.
+//
+//****************************************************************************
+#define PLT_CACHE_LINE_SIZE_MASK                0x000000FFL
+#define PLT_LATENCY_TIMER_MASK                  0x0000FF00L
+#define PLT_HEADER_TYPE_MASK                    0x00FF0000L
+#define PLT_BIST_MASK                           0xFF000000L
+#define PLT_CACHE_LINE_SIZE_SHIFT               0L
+#define PLT_LATENCY_TIMER_SHIFT                 8L
+#define PLT_HEADER_TYPE_SHIFT                   16L
+#define PLT_BIST_SHIFT                          24L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PCI base address registers.
+//
+//****************************************************************************
+#define PBAR_MEMORY_SPACE_INDICATOR             0x00000001L
+#define PBAR_LOCATION_TYPE_MASK                 0x00000006L
+#define PBAR_NOT_PREFETCHABLE                   0x00000008L
+#define PBAR_ADDRESS_MASK                       0xFFFFFFF0L
+#define PBAR_LOCATION_TYPE_SHIFT                1L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PCI subsystem ID/subsystem
+// vendor ID register.
+//
+//****************************************************************************
+#define PSS_SUBSYSTEM_VENDOR_ID_MASK            0x0000FFFFL
+#define PSS_SUBSYSTEM_ID_MASK                   0xFFFF0000L
+#define PSS_SUBSYSTEM_VENDOR_ID_SHIFT           0L
+#define PSS_SUBSYSTEM_ID_SHIFT                  16L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PCI interrupt register.
+//
+//****************************************************************************
+#define PI_LINE_MASK                            0x000000FFL
+#define PI_PIN_MASK                             0x0000FF00L
+#define PI_MIN_GRANT_MASK                       0x00FF0000L
+#define PI_MAX_LATENCY_MASK                     0xFF000000L
+#define PI_LINE_SHIFT                           0L
+#define PI_PIN_SHIFT                            8L
+#define PI_MIN_GRANT_SHIFT                      16L
+#define PI_MAX_LATENCY_SHIFT                    24L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the host interrupt status
+// register.
+//
+//****************************************************************************
+#define HISR_HVOLMASK                            0x00000003L
+#define HISR_VDNI                                0x00000001L
+#define HISR_VUPI                                0x00000002L
+#define HISR_GP1I                                0x00000004L
+#define HISR_GP3I                                0x00000008L
+#define HISR_GPSI                                0x00000010L
+#define HISR_GPPI                                0x00000020L
+#define HISR_DMAI                                0x00040000L
+#define HISR_FIFOI                               0x00100000L
+#define HISR_HVOL                                0x00200000L
+#define HISR_MIDI                                0x00400000L
+#define HISR_SBINT                               0x00800000L
+#define HISR_INTENA                              0x80000000L
+#define HISR_DMA_MASK                            0x00000F00L
+#define HISR_FIFO_MASK                           0x0000F000L
+#define HISR_DMA_SHIFT                           8L
+#define HISR_FIFO_SHIFT                          12L
+#define HISR_FIFO0                               0x00001000L
+#define HISR_FIFO1                               0x00002000L
+#define HISR_FIFO2                               0x00004000L
+#define HISR_FIFO3                               0x00008000L
+#define HISR_DMA0                                0x00000100L
+#define HISR_DMA1                                0x00000200L
+#define HISR_DMA2                                0x00000400L
+#define HISR_DMA3                                0x00000800L
+#define HISR_RESERVED                            0x40000000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the host interrupt control
+// register.
+//
+//****************************************************************************
+#define HICR_IEV                                 0x00000001L
+#define HICR_CHGM                                0x00000002L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the DMA Mode Register n
+// (DMRn)
+//
+//****************************************************************************
+#define DMRn_TR_MASK                             0x0000000CL
+#define DMRn_TR_SHIFT                            2L
+#define DMRn_AUTO                                0x00000010L
+#define DMRn_TR_READ                             0x00000008L
+#define DMRn_TR_WRITE                            0x00000004L
+#define DMRn_TYPE_MASK                           0x000000C0L
+#define DMRn_TYPE_SHIFT                          6L
+#define DMRn_SIZE8                               0x00010000L
+#define DMRn_MONO                                0x00020000L
+#define DMRn_BEND                                0x00040000L
+#define DMRn_USIGN                               0x00080000L
+#define DMRn_SIZE20                              0x00100000L
+#define DMRn_SWAPC                               0x00400000L
+#define DMRn_CBC                                 0x01000000L
+#define DMRn_TBC                                 0x02000000L
+#define DMRn_POLL                                0x10000000L
+#define DMRn_DMA                                 0x20000000L
+#define DMRn_FSEL_MASK                           0xC0000000L
+#define DMRn_FSEL_SHIFT                          30L
+#define DMRn_FSEL0                               0x00000000L
+#define DMRn_FSEL1                               0x40000000L
+#define DMRn_FSEL2                               0x80000000L
+#define DMRn_FSEL3                               0xC0000000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the DMA Command Register n
+// (DCRn)
+//
+//****************************************************************************
+#define DCRn_HTCIE                               0x00020000L
+#define DCRn_TCIE                                0x00010000L
+#define DCRn_MSK                                 0x00000001L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the FIFO Control 
+// register n.(FCRn)
+//
+//****************************************************************************
+#define FCRn_OF_MASK                            0x0000007FL
+#define FCRn_OF_SHIFT                           0L
+#define FCRn_SZ_MASK                            0x00007F00L
+#define FCRn_SZ_SHIFT                           8L
+#define FCRn_LS_MASK                            0x001F0000L
+#define FCRn_LS_SHIFT                           16L
+#define FCRn_RS_MASK                            0x1F000000L
+#define FCRn_RS_SHIFT                           24L
+#define FCRn_FEN                                0x80000000L
+#define FCRn_PSH                                0x20000000L
+#define FCRn_DACZ                               0x40000000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the serial port Power Management
+// control register.(SPMC)
+//
+//****************************************************************************
+#define SPMC_RSTN                               0x00000001L
+#define SPMC_ASYN                               0x00000002L
+#define SPMC_WUP1                               0x00000004L
+#define SPMC_WUP2                               0x00000008L
+#define SPMC_ASDI2E                             0x00000100L
+#define SPMC_ESSPD                              0x00000200L
+#define SPMC_GISPEN                             0x00004000L
+#define SPMC_GIPPEN                             0x00008000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the Configuration Load register.
+// (CFLR)
+//
+//****************************************************************************
+#define CFLR_CLOCK_SOURCE_MASK                  0x00000003L
+#define CFLR_CLOCK_SOURCE_AC97                  0x00000001L
+
+#define CFLR_CB0_MASK                            0x000000FFL
+#define CFLR_CB1_MASK                            0x0000FF00L
+#define CFLR_CB2_MASK                            0x00FF0000L
+#define CFLR_CB3_MASK                            0xFF000000L
+#define CFLR_CB0_SHIFT                           0L
+#define CFLR_CB1_SHIFT                           8L
+#define CFLR_CB2_SHIFT                           16L
+#define CFLR_CB3_SHIFT                           24L
+
+#define IOTCR_DMA0                              0x00000000L
+#define IOTCR_DMA1                              0x00000400L
+#define IOTCR_DMA2                              0x00000800L
+#define IOTCR_DMA3                              0x00000C00L
+#define IOTCR_CCLS                              0x00000100L
+#define IOTCR_PCPCI                             0x00000200L
+#define IOTCR_DDMA                              0x00000300L
+
+#define SBWBS_WBB                               0x00000080L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the SRC Slot Assignment Register
+// (SRCSA)
+//
+//****************************************************************************
+#define SRCSA_PLSS_MASK                         0x0000001FL
+#define SRCSA_PLSS_SHIFT                        0L
+#define SRCSA_PRSS_MASK                         0x00001F00L
+#define SRCSA_PRSS_SHIFT                        8L
+#define SRCSA_CLSS_MASK                         0x001F0000L
+#define SRCSA_CLSS_SHIFT                        16L
+#define SRCSA_CRSS_MASK                         0x1F000000L
+#define SRCSA_CRSS_SHIFT                        24L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the Sound System Power Management
+// register.(SSPM)
+//
+//****************************************************************************
+#define SSPM_FPDN                               0x00000080L
+#define SSPM_MIXEN                              0x00000040L
+#define SSPM_CSRCEN                             0x00000020L
+#define SSPM_PSRCEN                             0x00000010L
+#define SSPM_JSEN                               0x00000008L
+#define SSPM_ACLEN                              0x00000004L
+#define SSPM_FMEN                               0x00000002L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the Sound System Control
+// Register. (SSCR)
+//
+//****************************************************************************
+#define SSCR_SB                                 0x00000004L
+#define SSCR_HVC                                0x00000008L
+#define SSCR_LPFIFO                             0x00000040L
+#define SSCR_LPSRC                              0x00000080L
+#define SSCR_XLPSRC                             0x00000100L
+#define SSCR_MVMD                               0x00010000L
+#define SSCR_MVAD                               0x00020000L
+#define SSCR_MVLD                               0x00040000L
+#define SSCR_MVCS                               0x00080000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the Clock Control Register 1. 
+// (CLKCR1)
+//
+//****************************************************************************
+#define CLKCR1_DLLSS_MASK                       0x0000000CL
+#define CLKCR1_DLLSS_SHIFT                      2L
+#define CLKCR1_DLLP                             0x00000010L
+#define CLKCR1_SWCE                             0x00000020L
+#define CLKCR1_DLLOS                            0x00000040L
+#define CLKCR1_CKRA                             0x00010000L
+#define CLKCR1_CKRN                             0x00020000L
+#define CLKCR1_DLLRDY                           0x01000000L
+#define CLKCR1_CLKON                            0x02000000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the Sound Blaster Read Buffer
+// Status.(SBRBS)
+//
+//****************************************************************************
+#define SBRBS_RD_MASK                           0x0000007FL
+#define SBRBS_RD_SHIFT                          0L
+#define SBRBS_RBF                               0x00000080L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the serial port master control
+// register.(SERMC)
+//
+//****************************************************************************
+#define SERMC_MSPE                              0x00000001L
+#define SERMC_PTC_MASK                          0x0000000EL
+#define SERMC_PTC_SHIFT                         1L
+#define SERMC_PTC_AC97                          0x00000002L
+#define SERMC_PLB                               0x00000010L
+#define SERMC_PXLB                              0x00000020L
+#define SERMC_LOFV                              0x00080000L
+#define SERMC_SLB                               0x00100000L
+#define SERMC_SXLB                              0x00200000L
+#define SERMC_ODSEN1                            0x01000000L
+#define SERMC_ODSEN2                            0x02000000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the General Purpose I/O Register. 
+// (GPIOR)
+//
+//****************************************************************************
+#define GPIOR_VDNS                              0x00000001L
+#define GPIOR_VUPS                              0x00000002L
+#define GPIOR_GP1S                              0x00000004L
+#define GPIOR_GP3S                              0x00000008L
+#define GPIOR_GPSS                              0x00000010L
+#define GPIOR_GPPS                              0x00000020L
+#define GPIOR_GP1D                              0x00000400L
+#define GPIOR_GP3D                              0x00000800L
+#define GPIOR_VDNLT                             0x00010000L
+#define GPIOR_VDNPO                             0x00020000L
+#define GPIOR_VDNST                             0x00040000L
+#define GPIOR_VDNW                              0x00080000L
+#define GPIOR_VUPLT                             0x00100000L
+#define GPIOR_VUPPO                             0x00200000L
+#define GPIOR_VUPST                             0x00400000L
+#define GPIOR_VUPW                              0x00800000L
+#define GPIOR_GP1OE                             0x01000000L
+#define GPIOR_GP1PT                             0x02000000L
+#define GPIOR_GP1ST                             0x04000000L
+#define GPIOR_GP1W                              0x08000000L
+#define GPIOR_GP3OE                             0x10000000L
+#define GPIOR_GP3PT                             0x20000000L
+#define GPIOR_GP3ST                             0x40000000L
+#define GPIOR_GP3W                              0x80000000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the clock control register 1.
+//
+//****************************************************************************
+#define CLKCR1_PLLSS_MASK                       0x0000000CL
+#define CLKCR1_PLLSS_SERIAL                     0x00000000L
+#define CLKCR1_PLLSS_CRYSTAL                    0x00000004L
+#define CLKCR1_PLLSS_PCI                        0x00000008L
+#define CLKCR1_PLLSS_RESERVED                   0x0000000CL
+#define CLKCR1_PLLP                             0x00000010L
+#define CLKCR1_SWCE                             0x00000020L
+#define CLKCR1_PLLOS                            0x00000040L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the feature reporting register.
+//
+//****************************************************************************
+#define FRR_FAB_MASK                            0x00000003L
+#define FRR_MASK_MASK                           0x0000001CL
+#define FRR_ID_MASK                             0x00003000L
+#define FRR_FAB_SHIFT                           0L
+#define FRR_MASK_SHIFT                          2L
+#define FRR_ID_SHIFT                            12L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the serial port 1 configuration
+// register.
+//
+//****************************************************************************
+#define SERC1_VALUE                             0x00000003L
+#define SERC1_SO1EN                             0x00000001L
+#define SERC1_SO1F_MASK                         0x0000000EL
+#define SERC1_SO1F_CS423X                       0x00000000L
+#define SERC1_SO1F_AC97                         0x00000002L
+#define SERC1_SO1F_DAC                          0x00000004L
+#define SERC1_SO1F_SPDIF                        0x00000006L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the serial port 2 configuration
+// register.
+//
+//****************************************************************************
+#define SERC2_VALUE                             0x00000003L
+#define SERC2_SI1EN                             0x00000001L
+#define SERC2_SI1F_MASK                         0x0000000EL
+#define SERC2_SI1F_CS423X                       0x00000000L
+#define SERC2_SI1F_AC97                         0x00000002L
+#define SERC2_SI1F_ADC                          0x00000004L
+#define SERC2_SI1F_SPDIF                        0x00000006L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 control register.
+//
+//****************************************************************************
+#define ACCTL_ESYN                              0x00000002L
+#define ACCTL_VFRM                              0x00000004L
+#define ACCTL_DCV                               0x00000008L
+#define ACCTL_CRW                               0x00000010L
+#define ACCTL_TC                                0x00000040L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 status register.
+//
+//****************************************************************************
+#define ACSTS_CRDY                              0x00000001L
+#define ACSTS_VSTS                              0x00000002L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 output slot valid
+// register.
+//
+//****************************************************************************
+#define ACOSV_SLV3                              0x00000001L
+#define ACOSV_SLV4                              0x00000002L
+#define ACOSV_SLV5                              0x00000004L
+#define ACOSV_SLV6                              0x00000008L
+#define ACOSV_SLV7                              0x00000010L
+#define ACOSV_SLV8                              0x00000020L
+#define ACOSV_SLV9                              0x00000040L
+#define ACOSV_SLV10                             0x00000080L
+#define ACOSV_SLV11                             0x00000100L
+#define ACOSV_SLV12                             0x00000200L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 command address
+// register.
+//
+//****************************************************************************
+#define ACCAD_CI_MASK                           0x0000007FL
+#define ACCAD_CI_SHIFT                          0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 command data register.
+//
+//****************************************************************************
+#define ACCDA_CD_MASK                           0x0000FFFFL
+#define ACCDA_CD_SHIFT                          0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 input slot valid
+// register.
+//
+//****************************************************************************
+#define ACISV_ISV3                              0x00000001L
+#define ACISV_ISV4                              0x00000002L
+#define ACISV_ISV5                              0x00000004L
+#define ACISV_ISV6                              0x00000008L
+#define ACISV_ISV7                              0x00000010L
+#define ACISV_ISV8                              0x00000020L
+#define ACISV_ISV9                              0x00000040L
+#define ACISV_ISV10                             0x00000080L
+#define ACISV_ISV11                             0x00000100L
+#define ACISV_ISV12                             0x00000200L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 status address
+// register.
+//
+//****************************************************************************
+#define ACSAD_SI_MASK                           0x0000007FL
+#define ACSAD_SI_SHIFT                          0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 status data register.
+//
+//****************************************************************************
+#define ACSDA_SD_MASK                           0x0000FFFFL
+#define ACSDA_SD_SHIFT                          0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the I/O trap address and control
+// registers (all 12).
+//
+//****************************************************************************
+#define IOTAC_SA_MASK                           0x0000FFFFL
+#define IOTAC_MSK_MASK                          0x000F0000L
+#define IOTAC_IODC_MASK                         0x06000000L
+#define IOTAC_IODC_16_BIT                       0x00000000L
+#define IOTAC_IODC_10_BIT                       0x02000000L
+#define IOTAC_IODC_12_BIT                       0x04000000L
+#define IOTAC_WSPI                              0x08000000L
+#define IOTAC_RSPI                              0x10000000L
+#define IOTAC_WSE                               0x20000000L
+#define IOTAC_WE                                0x40000000L
+#define IOTAC_RE                                0x80000000L
+#define IOTAC_SA_SHIFT                          0L
+#define IOTAC_MSK_SHIFT                         16L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PC/PCI master enable
+// register.
+//
+//****************************************************************************
+#define PCPCIEN_EN                              0x00000001L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the joystick poll/trigger
+// register.
+//
+//****************************************************************************
+#define JSPT_CAX                                0x00000001L
+#define JSPT_CAY                                0x00000002L
+#define JSPT_CBX                                0x00000004L
+#define JSPT_CBY                                0x00000008L
+#define JSPT_BA1                                0x00000010L
+#define JSPT_BA2                                0x00000020L
+#define JSPT_BB1                                0x00000040L
+#define JSPT_BB2                                0x00000080L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the joystick control register.
+// The TBF bit has been moved from MIDSR register to JSCTL register bit 8.
+//
+//****************************************************************************
+#define JSCTL_SP_MASK                           0x00000003L
+#define JSCTL_SP_SLOW                           0x00000000L
+#define JSCTL_SP_MEDIUM_SLOW                    0x00000001L
+#define JSCTL_SP_MEDIUM_FAST                    0x00000002L
+#define JSCTL_SP_FAST                           0x00000003L
+#define JSCTL_ARE                               0x00000004L
+#define JSCTL_TBF                               0x00000100L
+
+
+//****************************************************************************
+//
+// The following defines are for the flags in the MIDI control register.
+//
+//****************************************************************************
+#define MIDCR_TXE                               0x00000001L
+#define MIDCR_RXE                               0x00000002L
+#define MIDCR_RIE                               0x00000004L
+#define MIDCR_TIE                               0x00000008L
+#define MIDCR_MLB                               0x00000010L
+#define MIDCR_MRST                              0x00000020L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the MIDI status register.
+//
+//****************************************************************************
+#define MIDSR_RBE                               0x00000080L
+#define MIDSR_RDA                               0x00008000L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the MIDI write port register.
+//
+//****************************************************************************
+#define MIDWP_MWD_MASK                          0x000000FFL
+#define MIDWP_MWD_SHIFT                         0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the MIDI read port register.
+//
+//****************************************************************************
+#define MIDRP_MRD_MASK                          0x000000FFL
+#define MIDRP_MRD_SHIFT                         0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the configuration interface
+// register.
+//
+//****************************************************************************
+#define CFGI_CLK                                0x00000001L
+#define CFGI_DOUT                               0x00000002L
+#define CFGI_DIN_EEN                            0x00000004L
+#define CFGI_EELD                               0x00000008L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the subsystem ID and vendor ID
+// register.
+//
+//****************************************************************************
+#define SSVID_VID_MASK                          0x0000FFFFL
+#define SSVID_SID_MASK                          0xFFFF0000L
+#define SSVID_VID_SHIFT                         0L
+#define SSVID_SID_SHIFT                         16L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the GPIO pin interface register.
+//
+//****************************************************************************
+#define GPIOR_VOLDN                             0x00000001L
+#define GPIOR_VOLUP                             0x00000002L
+#define GPIOR_SI2D                              0x00000004L
+#define GPIOR_SI2OE                             0x00000008L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 status register 2.
+//
+//****************************************************************************
+#define ACSTS2_CRDY                             0x00000001L
+#define ACSTS2_VSTS                             0x00000002L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 input slot valid
+// register 2.
+//
+//****************************************************************************
+#define ACISV2_ISV3                             0x00000001L
+#define ACISV2_ISV4                             0x00000002L
+#define ACISV2_ISV5                             0x00000004L
+#define ACISV2_ISV6                             0x00000008L
+#define ACISV2_ISV7                             0x00000010L
+#define ACISV2_ISV8                             0x00000020L
+#define ACISV2_ISV9                             0x00000040L
+#define ACISV2_ISV10                            0x00000080L
+#define ACISV2_ISV11                            0x00000100L
+#define ACISV2_ISV12                            0x00000200L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 status address
+// register 2.
+//
+//****************************************************************************
+#define ACSAD2_SI_MASK                          0x0000007FL
+#define ACSAD2_SI_SHIFT                         0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 status data register 2.
+//
+//****************************************************************************
+#define ACSDA2_SD_MASK                          0x0000FFFFL
+#define ACSDA2_SD_SHIFT                         0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the I/O trap control register.
+//
+//****************************************************************************
+#define IOTCR_ITD                               0x00000001L
+#define IOTCR_HRV                               0x00000002L
+#define IOTCR_SRV                               0x00000004L
+#define IOTCR_DTI                               0x00000008L
+#define IOTCR_DFI                               0x00000010L
+#define IOTCR_DDP                               0x00000020L
+#define IOTCR_JTE                               0x00000040L
+#define IOTCR_PPE                               0x00000080L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the I/O trap address and control
+// registers for Hardware Master Volume.  
+//
+//****************************************************************************
+#define IOTGP_SA_MASK                           0x0000FFFFL
+#define IOTGP_MSK_MASK                          0x000F0000L
+#define IOTGP_IODC_MASK                         0x06000000L
+#define IOTGP_IODC_16_BIT                       0x00000000L
+#define IOTGP_IODC_10_BIT                       0x02000000L
+#define IOTGP_IODC_12_BIT                       0x04000000L
+#define IOTGP_WSPI                              0x08000000L
+#define IOTGP_RSPI                              0x10000000L
+#define IOTGP_WSE                               0x20000000L
+#define IOTGP_WE                                0x40000000L
+#define IOTGP_RE                                0x80000000L
+#define IOTGP_SA_SHIFT                          0L
+#define IOTGP_MSK_SHIFT                         16L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the I/O trap address and control
+// registers for Sound Blaster
+//
+//****************************************************************************
+#define IOTSB_SA_MASK                           0x0000FFFFL
+#define IOTSB_MSK_MASK                          0x000F0000L
+#define IOTSB_IODC_MASK                         0x06000000L
+#define IOTSB_IODC_16_BIT                       0x00000000L
+#define IOTSB_IODC_10_BIT                       0x02000000L
+#define IOTSB_IODC_12_BIT                       0x04000000L
+#define IOTSB_WSPI                              0x08000000L
+#define IOTSB_RSPI                              0x10000000L
+#define IOTSB_WSE                               0x20000000L
+#define IOTSB_WE                                0x40000000L
+#define IOTSB_RE                                0x80000000L
+#define IOTSB_SA_SHIFT                          0L
+#define IOTSB_MSK_SHIFT                         16L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the I/O trap address and control
+// registers for FM.
+//
+//****************************************************************************
+#define IOTFM_SA_MASK                           0x0000FFFFL
+#define IOTFM_MSK_MASK                          0x000F0000L
+#define IOTFM_IODC_MASK                         0x06000000L
+#define IOTFM_IODC_16_BIT                       0x00000000L
+#define IOTFM_IODC_10_BIT                       0x02000000L
+#define IOTFM_IODC_12_BIT                       0x04000000L
+#define IOTFM_WSPI                              0x08000000L
+#define IOTFM_RSPI                              0x10000000L
+#define IOTFM_WSE                               0x20000000L
+#define IOTFM_WE                                0x40000000L
+#define IOTFM_RE                                0x80000000L
+#define IOTFM_SA_SHIFT                          0L
+#define IOTFM_MSK_SHIFT                         16L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PC/PCI request register.
+//
+//****************************************************************************
+#define PCPRR_RDC_MASK                         0x00000007L
+#define PCPRR_REQ                              0x00008000L
+#define PCPRR_RDC_SHIFT                        0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PC/PCI grant register.
+//
+//****************************************************************************
+#define PCPGR_GDC_MASK                         0x00000007L
+#define PCPGR_VL                               0x00008000L
+#define PCPGR_GDC_SHIFT                        0L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the PC/PCI Control Register.
+//
+//****************************************************************************
+#define PCPCR_EN                               0x00000001L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the debug index register.
+//
+//****************************************************************************
+#define DREG_REGID_MASK                         0x0000007FL
+#define DREG_DEBUG                              0x00000080L
+#define DREG_RGBK_MASK                          0x00000700L
+#define DREG_TRAP                               0x00000800L
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_TRAPX                              0x00001000L
+#endif
+#endif
+#define DREG_REGID_SHIFT                        0L
+#define DREG_RGBK_SHIFT                         8L
+#define DREG_RGBK_REGID_MASK                    0x0000077FL
+#define DREG_REGID_R0                           0x00000010L
+#define DREG_REGID_R1                           0x00000011L
+#define DREG_REGID_R2                           0x00000012L
+#define DREG_REGID_R3                           0x00000013L
+#define DREG_REGID_R4                           0x00000014L
+#define DREG_REGID_R5                           0x00000015L
+#define DREG_REGID_R6                           0x00000016L
+#define DREG_REGID_R7                           0x00000017L
+#define DREG_REGID_R8                           0x00000018L
+#define DREG_REGID_R9                           0x00000019L
+#define DREG_REGID_RA                           0x0000001AL
+#define DREG_REGID_RB                           0x0000001BL
+#define DREG_REGID_RC                           0x0000001CL
+#define DREG_REGID_RD                           0x0000001DL
+#define DREG_REGID_RE                           0x0000001EL
+#define DREG_REGID_RF                           0x0000001FL
+#define DREG_REGID_RA_BUS_LOW                   0x00000020L
+#define DREG_REGID_RA_BUS_HIGH                  0x00000038L
+#define DREG_REGID_YBUS_LOW                     0x00000050L
+#define DREG_REGID_YBUS_HIGH                    0x00000058L
+#define DREG_REGID_TRAP_0                       0x00000100L
+#define DREG_REGID_TRAP_1                       0x00000101L
+#define DREG_REGID_TRAP_2                       0x00000102L
+#define DREG_REGID_TRAP_3                       0x00000103L
+#define DREG_REGID_TRAP_4                       0x00000104L
+#define DREG_REGID_TRAP_5                       0x00000105L
+#define DREG_REGID_TRAP_6                       0x00000106L
+#define DREG_REGID_TRAP_7                       0x00000107L
+#define DREG_REGID_INDIRECT_ADDRESS             0x0000010EL
+#define DREG_REGID_TOP_OF_STACK                 0x0000010FL
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_REGID_TRAP_8                       0x00000110L
+#define DREG_REGID_TRAP_9                       0x00000111L
+#define DREG_REGID_TRAP_10                      0x00000112L
+#define DREG_REGID_TRAP_11                      0x00000113L
+#define DREG_REGID_TRAP_12                      0x00000114L
+#define DREG_REGID_TRAP_13                      0x00000115L
+#define DREG_REGID_TRAP_14                      0x00000116L
+#define DREG_REGID_TRAP_15                      0x00000117L
+#define DREG_REGID_TRAP_16                      0x00000118L
+#define DREG_REGID_TRAP_17                      0x00000119L
+#define DREG_REGID_TRAP_18                      0x0000011AL
+#define DREG_REGID_TRAP_19                      0x0000011BL
+#define DREG_REGID_TRAP_20                      0x0000011CL
+#define DREG_REGID_TRAP_21                      0x0000011DL
+#define DREG_REGID_TRAP_22                      0x0000011EL
+#define DREG_REGID_TRAP_23                      0x0000011FL
+#endif
+#endif
+#define DREG_REGID_RSA0_LOW                     0x00000200L
+#define DREG_REGID_RSA0_HIGH                    0x00000201L
+#define DREG_REGID_RSA1_LOW                     0x00000202L
+#define DREG_REGID_RSA1_HIGH                    0x00000203L
+#define DREG_REGID_RSA2                         0x00000204L
+#define DREG_REGID_RSA3                         0x00000205L
+#define DREG_REGID_RSI0_LOW                     0x00000206L
+#define DREG_REGID_RSI0_HIGH                    0x00000207L
+#define DREG_REGID_RSI1                         0x00000208L
+#define DREG_REGID_RSI2                         0x00000209L
+#define DREG_REGID_SAGUSTATUS                   0x0000020AL
+#define DREG_REGID_RSCONFIG01_LOW               0x0000020BL
+#define DREG_REGID_RSCONFIG01_HIGH              0x0000020CL
+#define DREG_REGID_RSCONFIG23_LOW               0x0000020DL
+#define DREG_REGID_RSCONFIG23_HIGH              0x0000020EL
+#define DREG_REGID_RSDMA01E                     0x0000020FL
+#define DREG_REGID_RSDMA23E                     0x00000210L
+#define DREG_REGID_RSD0_LOW                     0x00000211L
+#define DREG_REGID_RSD0_HIGH                    0x00000212L
+#define DREG_REGID_RSD1_LOW                     0x00000213L
+#define DREG_REGID_RSD1_HIGH                    0x00000214L
+#define DREG_REGID_RSD2_LOW                     0x00000215L
+#define DREG_REGID_RSD2_HIGH                    0x00000216L
+#define DREG_REGID_RSD3_LOW                     0x00000217L
+#define DREG_REGID_RSD3_HIGH                    0x00000218L
+#define DREG_REGID_SRAR_HIGH                    0x0000021AL
+#define DREG_REGID_SRAR_LOW                     0x0000021BL
+#define DREG_REGID_DMA_STATE                    0x0000021CL
+#define DREG_REGID_CURRENT_DMA_STREAM           0x0000021DL
+#define DREG_REGID_NEXT_DMA_STREAM              0x0000021EL
+#define DREG_REGID_CPU_STATUS                   0x00000300L
+#define DREG_REGID_MAC_MODE                     0x00000301L
+#define DREG_REGID_STACK_AND_REPEAT             0x00000302L
+#define DREG_REGID_INDEX0                       0x00000304L
+#define DREG_REGID_INDEX1                       0x00000305L
+#define DREG_REGID_DMA_STATE_0_3                0x00000400L
+#define DREG_REGID_DMA_STATE_4_7                0x00000404L
+#define DREG_REGID_DMA_STATE_8_11               0x00000408L
+#define DREG_REGID_DMA_STATE_12_15              0x0000040CL
+#define DREG_REGID_DMA_STATE_16_19              0x00000410L
+#define DREG_REGID_DMA_STATE_20_23              0x00000414L
+#define DREG_REGID_DMA_STATE_24_27              0x00000418L
+#define DREG_REGID_DMA_STATE_28_31              0x0000041CL
+#define DREG_REGID_DMA_STATE_32_35              0x00000420L
+#define DREG_REGID_DMA_STATE_36_39              0x00000424L
+#define DREG_REGID_DMA_STATE_40_43              0x00000428L
+#define DREG_REGID_DMA_STATE_44_47              0x0000042CL
+#define DREG_REGID_DMA_STATE_48_51              0x00000430L
+#define DREG_REGID_DMA_STATE_52_55              0x00000434L
+#define DREG_REGID_DMA_STATE_56_59              0x00000438L
+#define DREG_REGID_DMA_STATE_60_63              0x0000043CL
+#define DREG_REGID_DMA_STATE_64_67              0x00000440L
+#define DREG_REGID_DMA_STATE_68_71              0x00000444L
+#define DREG_REGID_DMA_STATE_72_75              0x00000448L
+#define DREG_REGID_DMA_STATE_76_79              0x0000044CL
+#define DREG_REGID_DMA_STATE_80_83              0x00000450L
+#define DREG_REGID_DMA_STATE_84_87              0x00000454L
+#define DREG_REGID_DMA_STATE_88_91              0x00000458L
+#define DREG_REGID_DMA_STATE_92_95              0x0000045CL
+#define DREG_REGID_TRAP_SELECT                  0x00000500L
+#define DREG_REGID_TRAP_WRITE_0                 0x00000500L
+#define DREG_REGID_TRAP_WRITE_1                 0x00000501L
+#define DREG_REGID_TRAP_WRITE_2                 0x00000502L
+#define DREG_REGID_TRAP_WRITE_3                 0x00000503L
+#define DREG_REGID_TRAP_WRITE_4                 0x00000504L
+#define DREG_REGID_TRAP_WRITE_5                 0x00000505L
+#define DREG_REGID_TRAP_WRITE_6                 0x00000506L
+#define DREG_REGID_TRAP_WRITE_7                 0x00000507L
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_REGID_TRAP_WRITE_8                 0x00000510L
+#define DREG_REGID_TRAP_WRITE_9                 0x00000511L
+#define DREG_REGID_TRAP_WRITE_10                0x00000512L
+#define DREG_REGID_TRAP_WRITE_11                0x00000513L
+#define DREG_REGID_TRAP_WRITE_12                0x00000514L
+#define DREG_REGID_TRAP_WRITE_13                0x00000515L
+#define DREG_REGID_TRAP_WRITE_14                0x00000516L
+#define DREG_REGID_TRAP_WRITE_15                0x00000517L
+#define DREG_REGID_TRAP_WRITE_16                0x00000518L
+#define DREG_REGID_TRAP_WRITE_17                0x00000519L
+#define DREG_REGID_TRAP_WRITE_18                0x0000051AL
+#define DREG_REGID_TRAP_WRITE_19                0x0000051BL
+#define DREG_REGID_TRAP_WRITE_20                0x0000051CL
+#define DREG_REGID_TRAP_WRITE_21                0x0000051DL
+#define DREG_REGID_TRAP_WRITE_22                0x0000051EL
+#define DREG_REGID_TRAP_WRITE_23                0x0000051FL
+#endif
+#endif
+#define DREG_REGID_MAC0_ACC0_LOW                0x00000600L
+#define DREG_REGID_MAC0_ACC1_LOW                0x00000601L
+#define DREG_REGID_MAC0_ACC2_LOW                0x00000602L
+#define DREG_REGID_MAC0_ACC3_LOW                0x00000603L
+#define DREG_REGID_MAC1_ACC0_LOW                0x00000604L
+#define DREG_REGID_MAC1_ACC1_LOW                0x00000605L
+#define DREG_REGID_MAC1_ACC2_LOW                0x00000606L
+#define DREG_REGID_MAC1_ACC3_LOW                0x00000607L
+#define DREG_REGID_MAC0_ACC0_MID                0x00000608L
+#define DREG_REGID_MAC0_ACC1_MID                0x00000609L
+#define DREG_REGID_MAC0_ACC2_MID                0x0000060AL
+#define DREG_REGID_MAC0_ACC3_MID                0x0000060BL
+#define DREG_REGID_MAC1_ACC0_MID                0x0000060CL
+#define DREG_REGID_MAC1_ACC1_MID                0x0000060DL
+#define DREG_REGID_MAC1_ACC2_MID                0x0000060EL
+#define DREG_REGID_MAC1_ACC3_MID                0x0000060FL
+#define DREG_REGID_MAC0_ACC0_HIGH               0x00000610L
+#define DREG_REGID_MAC0_ACC1_HIGH               0x00000611L
+#define DREG_REGID_MAC0_ACC2_HIGH               0x00000612L
+#define DREG_REGID_MAC0_ACC3_HIGH               0x00000613L
+#define DREG_REGID_MAC1_ACC0_HIGH               0x00000614L
+#define DREG_REGID_MAC1_ACC1_HIGH               0x00000615L
+#define DREG_REGID_MAC1_ACC2_HIGH               0x00000616L
+#define DREG_REGID_MAC1_ACC3_HIGH               0x00000617L
+#define DREG_REGID_RSHOUT_LOW                   0x00000620L
+#define DREG_REGID_RSHOUT_MID                   0x00000628L
+#define DREG_REGID_RSHOUT_HIGH                  0x00000630L
+
+//****************************************************************************
+//
+// The following defines are for the flags in the AC97 S/PDIF Control register.
+//
+//****************************************************************************
+#define SPDIF_CONTROL_SPDIF_EN                 0x00008000L
+#define SPDIF_CONTROL_VAL                      0x00004000L
+#define SPDIF_CONTROL_COPY                     0x00000004L
+#define SPDIF_CONTROL_CC0                      0x00000010L
+#define SPDIF_CONTROL_CC1                      0x00000020L
+#define SPDIF_CONTROL_CC2                      0x00000040L
+#define SPDIF_CONTROL_CC3                      0x00000080L
+#define SPDIF_CONTROL_CC4                      0x00000100L
+#define SPDIF_CONTROL_CC5                      0x00000200L
+#define SPDIF_CONTROL_CC6                      0x00000400L
+#define SPDIF_CONTROL_L                        0x00000800L
+
+#endif // _H_HWDEFS
diff -urN linux-2.2.17-pre16/drivers/sound/esssolo1.c linux/drivers/sound/esssolo1.c
--- linux-2.2.17-pre16/drivers/sound/esssolo1.c	Wed May  3 17:16:46 2000
+++ linux/drivers/sound/esssolo1.c	Mon Dec  3 22:11:10 2001
@@ -2169,7 +2169,7 @@
 	{ SOUND_MIXER_WRITE_LINE2, 0x4040 },
 	{ SOUND_MIXER_WRITE_RECLEV, 0x4040 },
 	{ SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
-	{ SOUND_MIXER_WRITE_MIC, 0x4040 }
+	{ SOUND_MIXER_WRITE_MIC, 0x0000 }
 };
 
 /*static*/ int __init init_solo1(void)
diff -urN linux-2.2.17-pre16/drivers/sound/sound_core.c linux/drivers/sound/sound_core.c
--- linux-2.2.17-pre16/drivers/sound/sound_core.c	Mon Dec  3 22:11:04 2001
+++ linux/drivers/sound/sound_core.c	Mon Dec  3 22:11:11 2001
@@ -452,6 +452,9 @@
 #ifdef CONFIG_SOUND_FUSION
 	cs_probe();
 #endif
+#ifdef CONFIG_SOUND_CS4281
+	cs4281_probe();
+#endif
 #ifdef CONFIG_SOUND_EMU10K1
 	init_emu10k1();
 #endif
diff -urN linux-2.2.17-pre16/drivers/sound/trident.c linux/drivers/sound/trident.c
--- linux-2.2.17-pre16/drivers/sound/trident.c	Mon Dec  3 22:11:04 2001
+++ linux/drivers/sound/trident.c	Mon Dec  3 22:11:11 2001
@@ -113,9 +113,11 @@
 #include <asm/hardirq.h>
 #include <linux/bitops.h>
 
+#include "dm.h"
+
 #include "trident.h"
 
-#define DRIVER_VERSION "0.14.5"
+#define DRIVER_VERSION "0.14.6a"
 
 /* magic numbers to protect our data structures */
 #define TRIDENT_CARD_MAGIC	0x5072696E /* "Prin" */
@@ -138,6 +140,10 @@
 /* minor number of /dev/swmodem (temporary, experimental) */
 #define SND_DEV_SWMODEM	7
 
+/* Size of the MIDI buffer */
+#define MIDIINBUF	256
+#define MIDIOUTBUF	256
+
 static const unsigned sample_size[] = { 1, 2, 2, 4 };
 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
 
@@ -156,6 +162,15 @@
 	{PCI_VENDOR_ID_ALI, PCI_DEVICE_ID_ALI_5451, "ALi Audio Accelerator"}
 };
 
+struct midi_stuff{
+	unsigned ird, iwr, icnt;
+	unsigned ord, owr, ocnt;
+	struct wait_queue *iwait;
+	struct wait_queue *owait;
+	unsigned char ibuf[MIDIINBUF];
+	unsigned char obuf[MIDIOUTBUF];
+};
+
 /* "software" or virtual channel, an instance of opened /dev/dsp */
 struct trident_state {
 	unsigned int magic;
@@ -267,15 +282,24 @@
 
 	/* soundcore stuff */
 	int dev_audio;
-
+	int dev_midi;
+	int dev_dmfm;
+	
+	/* Device locks */
+	int midi_on;
+	int dmfm_on;
+	
 	/* structures for abstraction of hardware facilities, codecs, banks and channels*/
 	struct ac97_codec *ac97_codec[NR_AC97];
 	struct trident_pcm_bank banks[NR_BANKS];
 	struct trident_state *states[NR_HW_CH];
+	struct midi_stuff midi;
 
 	/* hardware resources */
 	unsigned long iobase;
 	u32 irq;
+	unsigned long midi_io;
+	unsigned long synth_io;
 	
 	/* Function support */
 	struct trident_channel *(*alloc_pcm_channel)(struct trident_card *);
@@ -1269,6 +1293,35 @@
 
 }
 
+static void trident_handle_midi(struct trident_card *card)
+{
+	unsigned char ch;
+	int wake = 0;
+
+	while (!(inb(card->iobase + ALI_MPUR1) & 0x80)) {	
+		ch = inb(card->iobase + ALI_MPUR0);
+		if (card->midi.icnt < MIDIINBUF) {
+			card->midi.ibuf[card->midi.iwr] = ch;
+			card->midi.iwr = (card->midi.iwr + 1) % MIDIINBUF;
+			card->midi.icnt++;
+		}
+		wake = 1;
+	}
+	if (wake)
+		wake_up(&card->midi.iwait);
+	wake = 0;
+	while (!(inb(card->iobase + ALI_MPUR1) & 0x40) && card->midi.ocnt > 0) {
+		inb(card->iobase + ALI_MPUR0);
+		outb(card->midi.obuf[card->midi.ord], card->iobase + ALI_MPUR0);
+		card->midi.ord = (card->midi.ord + 1) % MIDIOUTBUF;
+		card->midi.ocnt--;
+		if (card->midi.ocnt < MIDIOUTBUF-16)
+			wake = 1;
+	}
+	if (wake)
+		wake_up(&card->midi.owait);
+}
+
 static void trident_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct trident_card *card = (struct trident_card *)dev_id;
@@ -1284,7 +1337,11 @@
 	if (event & ADDRESS_IRQ) {
 		card->address_interrupt(card);
 	}
-
+	
+	if(event & MPU401_IRQ) {
+		if(card->midi_on)
+			trident_handle_midi(card);
+	}
 	/* manually clear interrupt status, bad hardware design, blame T^2 */
 	outl((ST_TARGET_REACHED | MIXER_OVERFLOW | MIXER_UNDERFLOW),
 	     TRID_REG(card, T4D_MISCINT));
@@ -2018,6 +2075,385 @@
 	release:	trident_release,
 };
 
+/* --------------------------------------------------------------------- */
+
+/*
+ *	MIDI and direct synth support for the ALI 5451. These functions
+ *	are taken directly from Ching Ling Lee's original ALI only
+ *	driver.
+ */
+ 
+static ssize_t trident_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
+{
+	struct trident_card *card = (struct trident_card *)file->private_data;
+	ssize_t ret;
+	unsigned long flags;
+	unsigned ptr;
+	int cnt;
+	struct midi_stuff *midi;
+
+	if (ppos != &file->f_pos)
+		return -ESPIPE;
+	if (!access_ok(VERIFY_WRITE, buffer, count))
+		return -EFAULT;
+		
+	midi = &card->midi;
+	
+	ret = 0;
+	while (count > 0) {
+		spin_lock_irqsave(&card->lock, flags);
+		ptr = midi->ird;
+		cnt = MIDIINBUF - ptr;
+		if (midi->icnt < cnt)
+			cnt = midi->icnt;
+		spin_unlock_irqrestore(&card->lock, flags);
+		if (cnt > count)
+			cnt = count;
+		if (cnt <= 0) {
+			if (file->f_flags & O_NONBLOCK)
+				return ret ? ret : EAGAIN;
+			interruptible_sleep_on(&midi->iwait);
+			if (signal_pending(current))
+				return ret ? ret : -ERESTARTSYS;
+			continue;
+		}
+		if (copy_to_user(buffer, midi->ibuf + ptr, cnt))
+			return ret ? ret : -EFAULT;
+		ptr = (ptr + cnt) % MIDIINBUF;
+		spin_lock_irqsave(&card->lock, flags);
+		midi->ird = ptr;
+		midi->icnt -= cnt;
+		spin_unlock_irqrestore(&card->lock, flags);
+		count -= cnt;
+		buffer += cnt;
+		ret += cnt;
+	}
+	return ret;
+}
+
+static ssize_t trident_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
+{
+	struct trident_card *card = (struct trident_card *)file->private_data;
+	ssize_t ret;
+	unsigned long flags;
+	unsigned ptr;
+	int cnt;
+	struct midi_stuff *midi;
+
+	if (ppos != &file->f_pos)
+		return -ESPIPE;
+	if (!access_ok(VERIFY_READ, buffer, count))
+		return -EFAULT;
+		
+	midi = &card->midi;
+	
+	ret = 0;
+	while (count > 0) {
+		spin_lock_irqsave(&card->lock, flags);
+		ptr = midi->owr;
+		cnt = MIDIOUTBUF - ptr;
+		if (midi->ocnt + cnt > MIDIOUTBUF)
+			cnt = MIDIOUTBUF - midi->ocnt;
+		if (cnt <= 0)
+			trident_handle_midi(card);
+		spin_unlock_irqrestore(&card->lock, flags);
+		if (cnt > count)
+			cnt = count;
+		if (cnt <= 0) {
+			if (file->f_flags & O_NONBLOCK)
+				return ret ? ret : -EAGAIN;
+			interruptible_sleep_on(&midi->owait);
+			if (signal_pending(current))
+				return ret ? ret : -ERESTARTSYS;
+			continue;
+		}
+		if (copy_from_user(midi->obuf + ptr, buffer, cnt))
+			return ret ? ret : -EFAULT;
+		ptr = (ptr + cnt) % MIDIOUTBUF;
+		spin_lock_irqsave(&card->lock, flags);
+		midi->owr = ptr;
+		midi->ocnt += cnt;
+		spin_unlock_irqrestore(&card->lock, flags);
+		count -= cnt;
+		buffer += cnt;
+		ret += cnt;
+		spin_lock_irqsave(&card->lock, flags);
+		trident_handle_midi(card);
+		spin_unlock_irqrestore(&card->lock, flags);
+	}
+	return ret;
+}
+
+
+static unsigned int trident_midi_poll(struct file *file, struct poll_table_struct *wait)
+{
+	struct trident_card *card = (struct trident_card *)file->private_data;
+	unsigned long flags;
+	unsigned int mask = 0;
+
+	if (file->f_flags & FMODE_WRITE)
+		poll_wait(file, &card->midi.owait, wait);
+	if (file->f_flags & FMODE_READ)
+		poll_wait(file, &card->midi.iwait, wait);
+	spin_lock_irqsave(&card->lock, flags);
+	if (file->f_flags & FMODE_READ) {
+		if (card->midi.icnt > 0)
+			mask |= POLLIN | POLLRDNORM;
+	}
+	if (file->f_flags & FMODE_WRITE) {
+		if (card->midi.ocnt < MIDIOUTBUF)
+			mask |= POLLOUT | POLLWRNORM;
+	}
+	spin_unlock_irqrestore(&card->lock, flags);
+	return mask;
+}
+
+static int trident_midi_open(struct inode *inode, struct file *file)
+{
+	struct trident_card *card = devs;
+	struct midi_stuff *midi;
+	unsigned long flags;
+
+	while(card!=NULL)
+	{
+		if(card->midi_on == 0 && card->dev_midi!=-1)
+			break;
+		card=card->next;
+	}
+	if(card==NULL)
+		return -EBUSY;
+		
+	spin_lock_irqsave(&card->lock, flags);
+	card->midi_on = 1;
+	midi = &card->midi;
+	file->private_data = card;
+	if (file->f_mode & FMODE_READ) {
+		midi->ird = midi->iwr = midi->icnt = 0;
+	}
+	if (file->f_mode & FMODE_WRITE) {
+		midi->ord = midi->owr = midi->ocnt = 0;
+	}
+	spin_unlock_irqrestore(&card->lock, flags);
+	return 0;
+}
+
+static int trident_midi_release(struct inode *inode, struct file *file)
+{
+	struct trident_card *card = (struct trident_card *)file->private_data;
+        struct wait_queue wait = { current, NULL };
+	unsigned long flags;
+	unsigned count, tmo;
+
+	if (file->f_mode & FMODE_WRITE) {
+		current->state = TASK_INTERRUPTIBLE;
+		add_wait_queue(&card->midi.owait, &wait);
+		for (;;) {
+			spin_lock_irqsave(&card->lock, flags);
+			count = card->midi.ocnt;
+			spin_unlock_irqrestore(&card->lock, flags);
+			if (count <= 0)
+				break;
+			if (signal_pending(current))
+				break;
+			if (file->f_flags & O_NONBLOCK) {
+				remove_wait_queue(&card->midi.owait, &wait);
+				current->state = TASK_RUNNING;
+				return -EBUSY;
+			}
+			tmo = (count * HZ) / 3100;
+			if (!schedule_timeout(tmo ? : 1) && tmo)
+				printk(KERN_DEBUG "trident: midi timed out??\n");
+		}
+		remove_wait_queue(&card->midi.owait, &wait);
+		current->state = TASK_RUNNING;
+	}
+	spin_lock_irqsave(&card->lock, flags);
+	outb(0xff, card->iobase + ALI_MPUR1);
+	card->midi_on = 0;
+	spin_unlock_irqrestore(&card->lock, flags);
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+static /*const*/ struct file_operations trident_midi_fops = {
+	&trident_llseek,
+	&trident_midi_read,
+	&trident_midi_write,
+	NULL,  /* readdir */
+	&trident_midi_poll,
+	NULL,  /* ioctl */
+	NULL,  /* mmap */
+	&trident_midi_open,
+	NULL,	/* flush */
+	&trident_midi_release,
+	NULL,  /* fsync */
+	NULL,  /* fasync */
+	NULL,  /* check_media_change */
+	NULL,  /* revalidate */
+	NULL,  /* lock */
+};
+
+/* --------------------------------------------------------------------- */
+
+static int trident_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+	static const unsigned char op_offset[18] = {
+		0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+		0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
+		0x10, 0x11, 0x12, 0x13, 0x14, 0x15
+	};
+	struct trident_card *card = (struct trident_card *)file->private_data;
+	struct dm_fm_voice v;
+	struct dm_fm_note n;
+	struct dm_fm_params p;
+	unsigned int io;
+	unsigned int regb;
+
+	switch (cmd) {		
+	case FM_IOCTL_RESET:
+		for (regb = 0xb0; regb < 0xb9; regb++) {
+			outb(regb, card->synth_io);
+			outb(0, card->synth_io+1);
+			outb(regb, card->synth_io+2);
+			outb(0, card->synth_io+3);
+		}
+		return 0;
+
+	case FM_IOCTL_PLAY_NOTE:
+		if (copy_from_user(&n, (void *)arg, sizeof(n)))
+			return -EFAULT;
+		if (n.voice >= 18)
+			return -EINVAL;
+		if (n.voice >= 9) {
+			regb = n.voice - 9;
+			io = card->synth_io+2;
+		} else {
+			regb = n.voice;
+			io = card->synth_io;
+		}
+		outb(0xa0 + regb, io);
+		outb(n.fnum & 0xff, io+1);
+		outb(0xb0 + regb, io);
+		outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
+		return 0;
+
+	case FM_IOCTL_SET_VOICE:
+		if (copy_from_user(&v, (void *)arg, sizeof(v)))
+			return -EFAULT;
+		if (v.voice >= 18)
+			return -EINVAL;
+		regb = op_offset[v.voice];
+		io = card->synth_io + ((v.op & 1) << 1);
+		outb(0x20 + regb, io);
+		outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) | 
+		     ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
+		outb(0x40 + regb, io);
+		outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
+		outb(0x60 + regb, io);
+		outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
+		outb(0x80 + regb, io);
+		outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
+		outb(0xe0 + regb, io);
+		outb(v.waveform & 0x7, io+1);
+		if (n.voice >= 9) {
+			regb = n.voice - 9;
+			io = card->synth_io+2;
+		} else {
+			regb = n.voice;
+			io = card->synth_io;
+		}
+		outb(0xc0 + regb, io);
+		outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
+		     (v.connection & 1), io+1);
+		return 0;
+		
+	case FM_IOCTL_SET_PARAMS:
+		if (copy_from_user(&p, (void *)arg, sizeof(p)))
+			return -EFAULT;
+		outb(0x08, card->synth_io);
+		outb((p.kbd_split & 1) << 6, card->synth_io+1);
+		outb(0xbd, card->synth_io);
+		outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
+		     ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), card->synth_io+1);
+		return 0;
+
+	case FM_IOCTL_SET_OPL:
+		outb(4, card->synth_io+2);
+		outb(arg, card->synth_io+3);
+		return 0;
+
+	case FM_IOCTL_SET_MODE:
+		outb(5, card->synth_io+2);
+		outb(arg & 1, card->synth_io+3);
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+static int trident_dmfm_open(struct inode *inode, struct file *file)
+{
+	struct trident_card *card = devs;
+
+	file->private_data = card;
+	while(card!=NULL)
+	{
+		if(card->midi_on == 0 && card->dev_midi!=-1)
+			break;
+		card=card->next;
+	}
+	if(card==NULL)
+		return -EBUSY;
+	MOD_INC_USE_COUNT;		
+	card->dmfm_on = 1;
+
+	/* init the stuff */
+	outb(1, card->synth_io);
+	outb(0x20, card->synth_io+1); /* enable waveforms */
+	outb(4, card->synth_io+2);
+	outb(0, card->synth_io+3);  /* no 4op enabled */
+	outb(5, card->synth_io+2);
+	outb(1, card->synth_io+3);  /* enable OPL3 */
+	return 0;
+}
+
+static int trident_dmfm_release(struct inode *inode, struct file *file)
+{
+	struct trident_card *card = (struct trident_card *)file->private_data;
+	unsigned int regb;
+
+	for (regb = 0xb0; regb < 0xb9; regb++) {
+		outb(regb, card->synth_io);
+		outb(0, card->synth_io+1);
+		outb(regb, card->synth_io+2);
+		outb(0, card->synth_io+3);
+	}
+	card->dmfm_on = 0;
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+static /*const*/ struct file_operations trident_dmfm_fops = {
+	&trident_llseek,
+	NULL,  /* read */
+	NULL,  /* write */
+	NULL,  /* readdir */
+	NULL,  /* poll */
+	&trident_dmfm_ioctl,
+	NULL,  /* mmap */
+	&trident_dmfm_open,
+	NULL,	/* fl600
+	ush */
+	&trident_dmfm_release,
+	NULL,  /* fsync */
+	NULL,  /* fasync */
+	NULL,  /* check_media_change */
+	NULL,  /* revalidate */
+	NULL,  /* lock */
+};
+
+
 /* trident specific AC97 functions */
 /* Write AC97 codec registers */
 static void trident_ac97_set(struct ac97_codec *codec, u8 reg, u16 val)
@@ -2371,6 +2807,8 @@
 	memset(card, 0, sizeof(*card));
 
 	card->iobase = iobase;
+	card->midi_io = iobase + 0x20;
+	card->synth_io = iobase + 0x10;
 	card->pci_info = pci_info;
 	card->pci_id = pci_info->device;
 	card->irq = pci_dev->irq;
@@ -2424,6 +2862,31 @@
 		kfree(card);
 		return -ENODEV;
 	}
+	
+	if ((card->dev_midi = register_sound_midi(&trident_midi_fops, -1))<0)
+		printk(KERN_WARNING "trident: Unable to register midi.\n");
+	else
+	{
+		struct midi_stuff *midi = &card->midi;
+		init_waitqueue(&midi->iwait);
+		init_waitqueue(&midi->owait);
+		midi->ird = midi->iwr = midi->icnt = 0;
+		midi->ord = midi->owr = midi->ocnt = 0;
+		outb(0xbc, card->iobase+ALI_MPUR2);
+		
+		/* reset command */
+		while (inb(card->iobase + ALI_MPUR1) & 0x40);
+		outb(0xff, card->iobase + ALI_MPUR1);
+		while (inb(card->iobase + ALI_MPUR1) & 0x80);
+		while ((inb(card->iobase + ALI_MPUR0) != 0xfe) && (inb(card->iobase+ALI_MPUR1) != 0x10)) 
+			while (inb(card->iobase + ALI_MPUR1) & 0x80);
+			
+		midi->ird = midi->iwr = midi->icnt = 0;
+	}
+		
+	if ((card->dev_dmfm = register_sound_special(&trident_dmfm_fops, 15))<0)
+		printk(KERN_WARNING "trident: Unable to register FM.\n");
+	
 	outl(0x00, TRID_REG(card, T4D_MUSICVOL_WAVEVOL));
 
 	if (card->pci_id == PCI_DEVICE_ID_ALI_5451) {
@@ -2455,7 +2918,7 @@
 	if (!pci_present())   /* No PCI bus in this machine! */
 		return -ENODEV;
  
-	printk(KERN_INFO "Trident 4DWave/SiS 7018 PCI Audio, version "
+	printk(KERN_INFO "Trident 4DWave/SiS 7018/Ali 5451 PCI Audio, version "
 	       DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
  
 	for (i = 0; i < sizeof (pci_audio_devices); i++) {
@@ -2497,6 +2960,10 @@
 				kfree (devs->ac97_codec[i]);
 			}
 		unregister_sound_dsp(devs->dev_audio);
+		if(devs->dev_midi!=-1)
+			unregister_sound_midi(devs->dev_midi);
+		if(devs->dev_dmfm!=-1)
+			unregister_sound_special(devs->dev_dmfm);
  
 		kfree(devs);
 		devs = devs->next;
diff -urN linux-2.2.17-pre16/drivers/sound/trident.h linux/drivers/sound/trident.h
--- linux-2.2.17-pre16/drivers/sound/trident.h	Wed Jun  7 14:26:43 2000
+++ linux/drivers/sound/trident.h	Mon Dec  3 22:11:11 2001
@@ -246,6 +246,13 @@
 	ST_IRQ_EN       = 0x00800000, ACGPIO_IRQ      = 0x01000000
 };
 
+enum ali_mpuports {
+	ALI_MPUR0=0x20,
+	ALI_MPUR1=0x21,
+	ALI_MPUR2=0x22,
+	ALI_MPUR3=0x23
+};
+
 #define TRID_REG( trident, x ) ( (trident) -> iobase + (x) )
 
 #define VALIDATE_MAGIC(FOO,MAG)				\
diff -urN linux-2.2.17-pre16/include/asm-alpha/bitops.h linux/include/asm-alpha/bitops.h
--- linux-2.2.17-pre16/include/asm-alpha/bitops.h	Sat May 22 13:42:53 1999
+++ linux/include/asm-alpha/bitops.h	Mon Dec  3 22:11:11 2001
@@ -271,6 +271,8 @@
 	tmp = *p;
 found_first:
 	tmp |= ~0UL << size;
+	if (tmp == ~0UL)        /* Are any bits zero? */
+		return result + size; /* Nope. */
 found_middle:
 	return result + ffz(tmp);
 }
diff -urN linux-2.2.17-pre16/include/asm-sparc/bitops.h linux/include/asm-sparc/bitops.h
--- linux-2.2.17-pre16/include/asm-sparc/bitops.h	Sun Oct  4 10:22:44 1998
+++ linux/include/asm-sparc/bitops.h	Mon Dec  3 22:11:11 2001
@@ -1,4 +1,4 @@
-/* $Id: bitops.h,v 1.54 1998/09/21 05:07:34 jj Exp $
+/* $Id: bitops.h,v 1.54.2.1 2000/08/10 23:50:04 davem Exp $
  * bitops.h: Bit string operations on the Sparc.
  *
  * Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
@@ -240,6 +240,8 @@
 
 found_first:
 	tmp |= ~0UL << size;
+	if (tmp == ~0UL)        /* Are any bits zero? */
+		return result + size; /* Nope. */
 found_middle:
 	return result + ffz(tmp);
 }
@@ -387,7 +389,11 @@
 	tmp = *p;
 
 found_first:
-	return result + ffz(__swab32(tmp) | (~0UL << size));
+	tmp = __swab32(tmp) | (~0UL << size);
+	if (tmp == ~0UL)        /* Are any bits zero? */
+		return result + size; /* Nope. */
+	return result + ffz(tmp);
+
 found_middle:
 	return result + ffz(__swab32(tmp));
 }
diff -urN linux-2.2.17-pre16/include/asm-sparc64/bitops.h linux/include/asm-sparc64/bitops.h
--- linux-2.2.17-pre16/include/asm-sparc64/bitops.h	Wed Mar 10 16:53:38 1999
+++ linux/include/asm-sparc64/bitops.h	Mon Dec  3 22:11:11 2001
@@ -1,4 +1,4 @@
-/* $Id: bitops.h,v 1.26 1999/01/07 14:14:15 jj Exp $
+/* $Id: bitops.h,v 1.26.2.1 2000/08/10 23:50:04 davem Exp $
  * bitops.h: Bit string operations on the V9.
  *
  * Copyright 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
@@ -273,6 +273,8 @@
 
 found_first:
 	tmp |= ~0UL << size;
+	if (tmp == ~0UL)        /* Are any bits zero? */
+		return result + size; /* Nope. */
 found_middle:
 	return result + ffz(tmp);
 }
@@ -369,6 +371,8 @@
 	tmp = __swab64p(p);
 found_first:
 	tmp |= (~0UL << size);
+	if (tmp == ~0UL)        /* Are any bits zero? */
+		return result + size; /* Nope. */
 found_middle:
 	return result + ffz(tmp);
 }
diff -urN linux-2.2.17-pre16/net/core/dev.c linux/net/core/dev.c
--- linux-2.2.17-pre16/net/core/dev.c	Mon Dec  3 22:11:04 2001
+++ linux/net/core/dev.c	Mon Dec  3 22:11:11 2001
@@ -460,6 +460,10 @@
 	if (!(dev->flags&IFF_UP))
 		return 0;
 
+	/* If the device is a slave we should not touch it*/
+	if(dev->flags&IFF_SLAVE)
+		return -EBUSY;
+                                
 	dev_deactivate(dev);
 
 	dev_lock_wait();
